仅供个人纪录！！！
什么是网表文件？
在vivado中执行综合后即可生成网表文件，简单来说网表文件是对电路设计逻辑结构的描述，如网表由单元（cell）、引脚（pin）、端口（port）和网络（Net）构成。
综合之后Open Synthesis Design可以看到这样一个窗口，这就是记录了电路的网表信息。
如何导出网表文件？
如要导出网表信息，首先在综合前在Tools->Settings->Synthesis中进行设置，Option中这一项设置为
full，意思是模块综合后的层级结构全部为平层，只剩下顶层。看到一个解释说是为了打平整个设计，防止别人看到模块层次。选择full和默认选项rebuilt，后续网表再导入到别的项目时，综合出的结果不一样。
因为Vivado在综合时会自动将顶层的I/O口插入buffer，设置-mode out_of_context属性，表示在该级不插入任何I/O buffer。
设置好后进行综合，以如下代码为例：
module test(
input a0,
input a1,
input a2,
input a3,
input a4,
input a5,
output y
);
assign y = a0 & a1 & a2 & a3 & a4 & a5;
endmodule
综合后可以看到，代码被综合成了一个LUT6查找表。
在TCL console中输入指令来导出网表文件
- 导出空壳引脚描述文件：
write_verilog -mode synth_stub E:/BaiduSyncdisk/FPGA01/LUT/test1.v
//***********************************************************************
module test(a0, a1, a2, a3, a4, a5, y)
/* synthesis syn_black_box black_box_pad_pin="a0,a1,a2,a3,a4,a5,y" */;
input a0;
input a1;
input a2;
input a3;
input a4;
input a5;
output y;
endmodule
- 若需调用仿真，改用如下指令：
write_verilog -mode funcsim E:/BaiduSyncdisk/FPGA01/LUT/test3.v
//***********************************************************************
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module test
(a0,
a1,
a2,
a3,
a4,
a5,
y);
input a0;
input a1;
input a2;
input a3;
input a4;
input a5;
output y;
wire a0;
wire a1;
wire a2;
wire a3;
wire a4;
wire a5;
wire y;
LUT6 #(
.INIT(64'h8000000000000000))
y_INST_0
(.I0(a5),
.I1(a0),
.I2(a2),
.I3(a1),
.I4(a4),
.I5(a3),
.O(y));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
- 不指定-mode导出verilog代码（应该相当于综合后的电路代码）：
write_verilog E:/BaiduSyncdisk/FPGA01/LUT/test3.v
//**********************************************************
`timescale 1 ps / 1 ps
(* STRUCTURAL_NETLIST = "yes" *)
module test
(a0,
a1,
a2,
a3,
a4,
a5,
y);
input a0;
input a1;
input a2;
input a3;
input a4;
input a5;
output y;
wire a0;
wire a1;
wire a2;
wire a3;
wire a4;
wire a5;
wire y;
LUT6 #(
.INIT(64'h8000000000000000))
y_INST_0
(.I0(a5),
.I1(a0),
.I2(a2),
.I3(a1),
.I4(a4),
.I5(a3),
.O(y));
endmodule
- 导出综合后的网表文件
若不含Xilinx IP
write_edif E:/BaiduSyncdisk/FPGA01/LUT/test.edf
若含Xilinx IP
write_edif -security_mode all E:/BaiduSyncdisk/FPGA01/LUT/test2.edf
//**************************************************************************
(edif test
(edifversion 2 0 0)
(edifLevel 0)
(keywordmap (keywordlevel 0))
(status
(written
(timeStamp 2023 02 06 11 09 52)
(program "Vivado" (version "2018.3"))
(comment "Built on 'Thu Dec 6 23:38:27 MST 2018'")
(comment "Built by 'xbuild'")
)
)
(Library hdi_primitives
(edifLevel 0)
(technology (numberDefinition ))
(cell LUT6 (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port I4 (direction INPUT))
(port I5 (direction INPUT))
)
)
)
(cell INV (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
)
(Library work
(edifLevel 0)
(technology (numberDefinition ))
(cell test (celltype GENERIC)
(view test (viewtype NETLIST)
(interface
(port a0 (direction INPUT))
(port a1 (direction INPUT))
(port a2 (direction INPUT))
(port a3 (direction INPUT))
(port a4 (direction INPUT))
(port a5 (direction INPUT))
(port y (direction OUTPUT))
)
(contents
(instance y_INST_0 (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
(property INIT (string "64'h8000000000000000"))
)
(net a0 (joined
(portref I1 (instanceref y_INST_0))
(portref a0)
)
)
(net a1 (joined
(portref I3 (instanceref y_INST_0))
(portref a1)
)
)
(net a2 (joined
(portref I2 (instanceref y_INST_0))
(portref a2)
)
)
(net a3 (joined
(portref I5 (instanceref y_INST_0))
(portref a3)
)
)
(net a4 (joined
(portref I4 (instanceref y_INST_0))
(portref a4)
)
)
(net a5 (joined
(portref I0 (instanceref y_INST_0))
(portref a5)
)
)
(net y (joined
(portref O (instanceref y_INST_0))
(portref y)
)
)
)
)
)
)
(comment "Reference To The Cell Of Highest Level")
(design test
(cellref test (libraryref work))
(property XLNX_PROJ_DIR (string "E:/BaiduSyncdisk/FPGA01/LUT"))
(property part (string "xc7vx485tffg1157-1"))
)
)
生成的网表文件如何导入Vivado?
因为网表文件包含了电路的逻辑结构，各种元件以及连线，因此可以直接用来生成电路、仿真以及生成比特流文件。注意的是仿真分为RTL仿真以及门级仿真，使用网表文件不能进行RTL仿真，因为里面描述的都是门级原语。文章来源：https://www.toymoban.com/news/detail-403723.html
把生成的引脚描述文件和edf文件导入到新项目中，并写一个top模块进行调用，可以看到电路图如图所示。
一开始顶层文件没有加输入输出引脚，只是调用了一下test，结果综合出来没有结果。加了输入输出之后，综合结果如下。
综合后，就可以进行门级功能仿真了。Implementation后，可以查看在FPGA中对应的结构（下图另一个project的截图，仅供展示）。
文章来源地址https://www.toymoban.com/news/detail-403723.html
到了这里，关于Vivado生成网表文件的文章就介绍完了。如果您还想了解更多内容，请在右上角搜索TOY模板网以前的文章或继续浏览下面的相关文章，希望大家以后多多支持TOY模板网！
