在实际Layout过程中，差分对上往往串接有电阻，电容或共模电感。这时候就需要创建Xnet。那么Allegro如何创建Xnet呢？
具体操作如下：
1、点击菜单 Analyze（分析）→Model Assigment（模型分配），如下图所示
2、跳出SI Design Audit对话框，直接点OK，如下图所示
3、接着跳出下面的对话框，也不用管，点是
4、然后跳出下面对话框（Signal Model AssIgnment），如下图所示
5、不要关闭此窗口，此时选中要设置的差分对内串接的阻容器件，差分是两个阻容器件，先选其中的一个，等一个设置完成后，再设置另一个。选中该阻容器件后，Assignment对话框会自动定位到该器件的模型，如下图所示
6、然后单击Create Model，选择默认的Create ESpiceDevice model，如下图所示
7、跳出如下对话框
参数解释：
ModelName：输入产生Model的名字。
Circuit type（选择类型）：电阻，电容或共模电感。
Value（值）：一般填100。
Single Pins（各Pin的连接顺序，中间为空格）：这里需要注意零件的 pin脚排列1 2 3 4，就是：1和2是一个电阻，3和4是一个电阻，如下图。如果是普通电阻电容，Single Pins就填1空格2。
Common Pin：不用管，空着。
输入好后点击OK，就完成了Model的建立。点击OK退出即可。
8、然后在PCB中Show Element查看该器件的属性，可以发现该电阻两边的Net都有了Xnet属性，此时再点击另一个阻容器件，做同样的设置，因为差分对是一对。设置完成后该差分对的Xnet就设置好了。其它差分对设置方法同样设置。
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Allegro provides a good and interactive working interface and powerful functions, and its front-end products Cadence, OrCAD, Capture, the combination of high-speed, high-density, multi-layer complex PCB design routing provides the most perfect solution.
Allegro has perfect Constraint Settings, users only need to set the wiring rules according to the requirements, and the design requirements of the wiring can be achieved without violating the DRC when routing, thus saving the tedious manual inspection time and improving the work efficiency!
It can also define parameters such as minimum wire-width or wire-length to meet the needs of today's high-speed circuit board wiring.
Constraint Manger provides a simple interface for users to set and view Constraint declarations.
Its combination with Capture allows E.E. electronics engineers to set up regular data when drawing a circuit diagram and bring it with them to the Allegro working environment, where it can be automatically processed and checked when placing parts and wiring. The empirical values of these regular data can be reused for the same nature of the circuit board design.
In addition to the above functions, Allegro's powerful automatic push and stick line and perfect automatic repair line function provide users with great convenience;
The powerful mapping function can provide multiple users to deal with a complex board at the same time, thus greatly improving the work efficiency.
Or use the optional graph cutting function to cut the circuit board into various blocks, so that each block has a full-time person at the same time to design, to achieve the purpose of the same graph design and can shorten the time course.
After renaming, online interchange and modifying logic during routing, users can easily return to Capture wiring diagram, and update the wiring diagram to Allegro after modification.文章来源：https://www.toymoban.com/news/detail-427663.html
Users can also click and modify objects between Capture and Allegro.文章来源地址https://www.toymoban.com/news/detail-427663.html
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