目录
1.题意描述
2.利用摩尔型状态机求解
3.利用米利型状态机求解
4.摩尔型状态机与米利型状态机的区别
1.题意描述
用状态机检测“1101”序列，当检测到后将o_valid标志信号拉高。考虑序列叠加情况，即“1101101101”将会识别出3个“1101”
2.利用摩尔型状态机求解
摩尔型状态机：输出只与当前状态有关，与当前输入无关
摩尔型状态机状态定义：IDLE, S_1,S_11,S_110,S_1101
摩尔型状态机状态转移图：
摩尔型状态机RTL代码:
module sequence_test_more(
i_clk ,
i_rst_n ,
i_data ,
o_valid
);
input i_clk ;
input i_rst_n ;
input i_data ;
output o_valid ;
reg o_valid ;
parameter IDLE = 3'b000;
parameter S_1 = 3'b001;
parameter S_11 = 3'b010;
parameter S_110 = 3'b011;
parameter S_1101 = 3'b100;
reg [2:0] current_state ;
reg [2:0] next_state ;
always@(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
current_state <= #1 IDLE ;
else
current_state <= #1 next_state ;
end
always@(*)
begin
case(current_state)
IDLE :
if(i_data==1'b1)
next_state = S_1 ;
else
next_state = IDLE ;
S_1 :
if(i_data==1'b1)
next_state = S_11 ;
else
next_state = IDLE ;
S_11 :
if(i_data==1'b0)
next_state = S_110 ;
else
next_state = S_11 ;
S_110 :
if(i_data==1'b1)
next_state = S_1101 ;
else
next_state = IDLE ;
S_1101 :
if(i_data==1'b1)
next_state = S_11 ;
else
next_state = IDLE ;
default :
next_state = IDLE ;
endcase
end
always@(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
o_valid <= #1 1'b0 ;
else if(next_state==S_1101)
o_valid <= #1 1'b1 ;
else
o_valid <= #1 1'b0 ;
end
endmodule
仿真文件：输入序列11101101011010
`timescale 1ns/1ns
module test;
//************i_clk and i_rst_n*************
reg i_rst_n ;
reg i_clk ;
initial
begin
i_rst_n = 1'b0 ;
i_clk = 1'b0 ;
#20;
i_rst_n = 1'b1 ;
end
always #5 i_clk<=~i_clk;
//************define******************
reg i_data ;
wire o_valid ;
//************instance****************
sequence_test_more U1(
.i_clk (i_clk ),
.i_rst_n (i_rst_n),
.i_data (i_data ),
.o_valid (o_valid)
);
//************main source*************
parameter TEST_DATA = 14'b1110_1101_0110_10;
initial
begin
i_data = 1'b0;
#50;
@(posedge i_clk)
i_data <=#1 TEST_DATA[13];
@(posedge i_clk)
i_data <=#1 TEST_DATA[12];
@(posedge i_clk)
i_data <=#1 TEST_DATA[11];
@(posedge i_clk)
i_data <=#1 TEST_DATA[10];
@(posedge i_clk)
i_data <=#1 TEST_DATA[9];
@(posedge i_clk)
i_data <=#1 TEST_DATA[8];
@(posedge i_clk)
i_data <=#1 TEST_DATA[7];
@(posedge i_clk)
i_data <=#1 TEST_DATA[6];
@(posedge i_clk)
i_data <=#1 TEST_DATA[5];
@(posedge i_clk)
i_data <=#1 TEST_DATA[4];
@(posedge i_clk)
i_data <=#1 TEST_DATA[3];
@(posedge i_clk)
i_data <=#1 TEST_DATA[2];
@(posedge i_clk)
i_data <=#1 TEST_DATA[1];
@(posedge i_clk)
i_data <=#1 TEST_DATA[0];
#50;
$finish;
end
//***************fsdb****************
initial
begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(0,test);
end
endmodule
仿真波形：
3.利用米利型状态机求解
米利型状态机：输出不仅当前状态有关，还与当前输入有关
米利型状态机状态定义：IDLE, S_1,S_11,S_110
米利型状态机状态转移图：
米利型状态机RTL代码:
module sequence_test_mely(
i_clk ,
i_rst_n ,
i_data ,
o_valid
);
input i_clk ;
input i_rst_n ;
input i_data ;
output o_valid ;
reg o_valid ;
parameter IDLE = 3'b000;
parameter S_1 = 3'b001;
parameter S_11 = 3'b010;
parameter S_110 = 3'b011;
//parameter S_1101 = 3'b100;
reg [2:0] current_state ;
reg [2:0] next_state ;
always@(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
current_state <= #1 IDLE ;
else
current_state <= #1 next_state ;
end
always@(*)
begin
case(current_state)
IDLE :
if(i_data==1'b1)
next_state = S_1 ;
else
next_state = IDLE ;
S_1 :
if(i_data==1'b1)
next_state = S_11 ;
else
next_state = IDLE ;
S_11 :
if(i_data==1'b0)
next_state = S_110 ;
else
next_state = S_11 ;
S_110 :
if(i_data==1'b1)
next_state = S_1 ;
else
next_state = IDLE ;
default :
next_state = IDLE ;
endcase
end
always@(posedge i_clk or negedge i_rst_n)
begin
if(!i_rst_n)
o_valid <= #1 1'b0;
else if((current_state==S_110) && (i_data == 1'b1))
o_valid <= #1 1'b1 ;
else
o_valid <= #1 1'b0 ;
end
endmodule仿真文件：输入序列11101101011010（与摩尔型仿真激励相同）
仿真波形：
文章来源：https://www.toymoban.com/news/detail-455996.html
4.摩尔型状态机与米利型状态机的区别
在状态定义上米利型状态机比摩尔型状态机少一个状态。文章来源地址https://www.toymoban.com/news/detail-455996.html
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