FPGA中Verilog的单首音乐播放器代码，简洁易懂

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利用数控分频器设计硬件乐曲演奏电路，利用蜂鸣器播放《我和我的祖国》

分频器模块：

module div(iclk_50,rst,addr,clk_4);
input iclk_50;
input rst;
output [8:0]addr;
output clk_4;

reg clk_4;
reg [8:0]addr;
reg [31:0]count_4;

always@(posedge iclk_50 or negedge rst)
begin
if(!rst)
begin
clk_4=1'b0;
count_4<=32'd0;
end
else if(count_4==50000000/4*2-1)
begin
clk_4=~clk_4;
count_4<=32'd0;
end
else
count_4<=count_4+32'd1;
end
always@(posedge clk_4 or negedge rst)
begin
if(!rst)
addr<=9'd0;
else if(addr==9'd420)
addr<=9'd0;
else addr<=addr+9'd1;
end
endmodule
音频产生模块：

module ToneTaba(iclk_50,code,speaker);
input iclk_50;
input [4:0]code;
output speaker;
reg [17:0]Tone;
reg [17:0]cnt;
reg clk_tmp;
always@(posedge iclk_50)
begin
case(code)
5'd0:Tone<=134;
5'd1:Tone<=191132;
5'd2:Tone<=170242;
5'd3:Tone<=151700;
5'd4:Tone<=143184;
5'd5:Tone<=127552;
5'd6:Tone<=113636;
5'd7:Tone<=101236;
5'd8:Tone<=95548;
5'd9:Tone<=85136;
5'd10:Tone<=75838;
5'd11:Tone<=71582;
5'd12:Tone<=65776;
5'd13:Tone<=56818;
5'd14:Tone<=50618;
5'd15:Tone<=47824;
5'd16:Tone<=42564;
5'd17:Tone<=37992;
5'd18:Tone<=35794;
5'd19:Tone<=31888;
5'd20:Tone<=28409;
5'd21:Tone<=25310;
endcase;
if(cnt==Tone/2-1)
begin
clk_tmp=~clk_tmp;
cnt<=0;
end
else
cnt<=cnt+1;
end
assign speaker=clk_tmp;
endmodule