问题
在Vivado中进行FPGA的综合无误后，实现时出现报错如下：
![FPGA实现问题：[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk](https://imgs.yssmx.com/Uploads/2023/06/506735-1.png)
[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 500.000 MHz (CLKIN1_PERIOD, net clk_in1_clock) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y1 (cell inst_clock/inst/mmcm_adv_inst) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (20.000000), multiplication factor CLKFBOUT_MULT_F (10.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
其大意为约束文件中设定的时钟周期超过了IP核中的设备周期
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![【常见 error】Vivado生成比特流时报错[DRC NSTD-1]和[DRC UCIO-1]](https://imgs.yssmx.com/Uploads/2024/02/781543-1.png)
