1.Module
module top_module ( input a, input b, output out );
mod_a U1(.in1(a), .in2(b) , .out(out));
endmodule
2.Module pos
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a u_mod_a(
out1,
out2,
a,
b,
c,
d
);
endmodule
3.Module name
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a U1(.in1(a),.in2(b),.in3(c),.in4(d),.out1(out1),.out2(out2));
endmodule
4.Module shift
module top_module ( input clk, input d, output q );
wire q1,q2;
my_dff U1(.clk(clk),.d(d),.q(q1));
my_dff U2(.clk(clk),.d(q1),.q(q2));
my_dff U3(.clk(clk),.d(q2),.q(q));
endmodule
5.Module shift8
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire[7:0] q1,q2,q3;
my_dff8 U1(.clk(clk),.d(d),.q(q1));
my_dff8 U2(.clk(clk),.d(q1),.q(q2));
my_dff8 U3(.clk(clk),.d(q2),.q(q3));
always@(*) begin
case(sel)
2'b11:q<=q3;
2'b10:q<=q2;
2'b01:q<=q1;
2'b00:q<=d;
endcase
end
endmodule
6.Module add
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire[15:0] sum1,sum2;
wire n;
add16 U1(.a(a[15:0]),.b(b[15:0]),.cin(0),.sum(sum1),.cout(n));
add16 U2(.a(a[31:16]),.b(b[31:16]),.cin(n),.sum(sum2));
assign sum={sum2,sum1};
endmodule
7.Module fadd
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);//
wire [15:0] sum1;
wire [15:0] sum2;
wire cout;
add16 add16_inst_l(
.a(a[15:0]),
.b(b[15:0]),
.cin('d0),
.cout(cout),
.sum(sum1)
);
add16 add16_inst_h(
.a(a[31:16]),
.b(b[31:16]),
.cin(cout),
.sum(sum2)
);
assign sum = {sum2,sum1};
endmodule
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign {cout,sum} = a+b+cin;
endmodule
8.Module cseladd
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire[15:0] sum0,sum1,sum2;
wire sel;
add16 U1(.a(a[15:0]),.b(b[15:0]),.cin(0),.cout(sel),.sum(sum0));
add16 U2(.a(a[31:16]),.b(b[31:16]),.cin(0),.sum(sum1));
add16 U3(.a(a[31:16]),.b(b[31:16]),.cin(1),.sum(sum2));
always@(*) begin
case(sel)
1'b0:sum={sum1,sum0};
1'b1:sum={sum2,sum0};
endcase
end
endmodule
9.Module addsub
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire n;
wire[15:0] sum0,sum1;
wire [31:0] nb;
assign nb={32{sub}}^b;
add16 U1(.a(a[15:0]),.b(nb[15:0]),.cin(sub),.cout(n),.sum(sum0));
add16 U2(.a(a[31:16]),.b(nb[31:16]),.cin(n),.sum(sum1));
assign sum={sum1,sum0};
endmodule
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