从IC版图Layout的视角看待VLSI从设计到流片、FAB制造 【VLSI】

一、什么是IC版图？

1. IC版图基础概念

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.

2. 工程师使用EDA、CAD工具完成IC版图的布局布线

Modern IC layout is done with the aid of IC layout editor software, mostly automatically using EDA、CAD tools, including place and route tools or schematic-driven layout tools. Typically this involves a library of standard cells（各种基础门电路就属于cell library）.

3. 经过设计和验证后输出GDSII

When all design and verification of IC Layout is complete, layout post processing is applied where the data is also translated into an industry-standard format, typically GDSII, and sent to a semiconductor foundry. The milestone completion of the layout process of sending this data to the foundry is now colloquially called “tapeout”. The foundry converts the data into mask data and uses it to generate the photomasks used in a photolithographic process of semiconductor device fabrication.

至此，IC版图的设计介绍结束。
下面介绍 IC版图 、 光刻机的光刻工艺 和 fab超净间的制造 之间的关系

4. 流片tape-out

Tape-out is the final phase of a design life cycle for a IC design (ASIC/SOC) before the manufacturing starts.

Tape-out is the final phase of a design life cycle for a IC design (ASIC/SOC) before the manufacturing starts. The tapeout is specifically the point at which the graphic for the photomask of the circuit is sent to the fabrication facility.

ps, Why this process is called “TAPE-OUT”? The term is kept for historical reasons when the data was actually transferred to the foundry physically shipping a tape with all the data. In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, an evolution derived from early days of printed circuit board (PCB) design.

5. Photolithography光刻

Photolithography is a process of transferring the pattern from mask to substrate, and shrink a mask pattern and project it onto the wafer.

Photolithography is the most common method for fabricating IC integrated circuits (“electronic chips”). It can create extremely small patterns, down to a few tens of nanometers in size. It provides precise control of the shape and size of the objects it creates and can create patterns over an entire wafer in a single step, quickly and with relatively low cost.

Mask 、Photomask和Photolithography光刻技术的关系

光刻（Photolithography）的输出是光刻胶上的图形，是需要一系列工艺的过程，是将掩模版上的图形(PHOTOMASK)转移光刻胶上的过程，是将IC版图的一些数据和结构临时“复制”到硅片上的过程。光刻利用曝光和显影在光刻胶层上“画上”需要的图形，这样获得的图形用作Etching（蚀刻）工艺或者implantation（我个人理解叫更深的掺杂doping）的mask。
CMOS工艺详见本文：CMOS PROCESS FLOW 简化版总结 CMOS制造工艺流程 后端版图

Photomasks, The image for the mask originates from a computerized data file. This data file is converted to a series of polygons and written onto a square of fused quartz substrate covered with a layer of chromium using a photolithographic process. A laser beam (laser writer) or a beam of electrons (e-beam writer) is used to expose the pattern defined by the data file and travels over the surface of the substrate in either a vector or raster scan manner. Where the photoresist on the mask is exposed, the chrome can be etched away, leaving a clear path for the illumination light in the stepper/scanner system to travel through.区分画版图时候的MASK，画版图的MASK可能只指的是某一类型的掩膜。

ps, Photolithography requires extremely clean operating conditions.

二、一名IC版图工程师的视角看待版图设计与芯片生产的关联

1. 版图设计 和 FAB工艺制作 的区别

The first thing we need to understand is，whotolithography is a process of transferring the pattern from mask to substrate. And Layout is drawing the masks used in the manufacturing process. So, during the layout designing, sequence of different layers in a mask layout is completely arbitrary, it does not have to follow the actual fabrication sequence.

Secondly，In the world of CAD tools, designers talks about the TOP view, which is known as LAYOUT of the design. Therefore most layout CAD tools use mask layers that are more intuitive to the layout designer, and map to the real mask later.
Most CAD systems use two methods to do circuit design: connectivity and geometry.

• The connectivity approach is used by every Schematic design system: you place components and draw connecting wires. The components remain connected, even when they move.
• The geometry approach is used by most Integrated Circuit (IC) layout systems: rectangles of “paint” are laid down on different layers to form the masks for chip fabrication.

Thirdly，The way that CAD software (eg. Magic, Cadence, Electric…) handles all types of circuit design is by viewing it as a collection of nodes and arcs, woven into a network.

• Nodes: The nodes are electrical components such as transistors, contacts, and logic gates. ! Nodes are connected together using wires(called arcs).
• Arcs / Lines are simply wires that connect two components.
• Ports are the connection sites on nodes where the wires connect.
• contacts is used to join different layerstogether.

2. 对比 绘制Layout 和 真实的制造工艺步骤

Potential confusion of “defining the masks for the logic cells” arises because we like to keep layout simple but maintain a “what you see is what you get” (WYSIWYG) approach. This means that the drawn layers do not correspond directly to the masks in all cases.

	Steps	3D视图
1	Draw N-select, N-well and P select layers
2	Draw Poly layer
3	Draw N+ Diffusion For NMOS. For PMOS Body Contact, Draw N-select, N+ diffusion
4	Draw P+ Diffusion for PMOS devices
5	Draw Metal Contact and Metal M1 which connect Contacts

什么是Active area？

• Active layer in a layout defines openings in the silicon-di-oxide covering the substrate.
• Active area defines the active regions of the chip it can be seen as the places where the think oxide layer will be grown and the thin oxide is basically the gate oxide for MOS transistors.
• Active mask defines p-type and n-type mosfet locations

什么是P-selet、N-selet？

• p-select covers p-type source/drain regions
• select mask must overlap active areas
• n-type ion implant creates n-type source/drain regions
• high temperature anneal repairs silicon lattice and causes diffusion of implanted ions

为什么N-select or P-select mask 比 Active mask 更大一些？

Why n-select or p-select mask is greater than the Active mask/layer？
You may be thinking that why n-select or p-select mask is greater than the Active mask/layer. Actually it depends on the alignment of the 2 masks. If p-select / n-select mask is properly aligned with the active layer mask then there is no need of any extra p-select around the Active layer. But to take precaution or avoiding any misalignment (which can stop to dope the active region with proper doping, either n type of p type), we keep the active layer mask smaller than the select layer mask.

为什么选择硅作为沟道材料？

Coating a silicon wafer with an insulating layer of silicon oxide so that electricity could reliably penetrate to the conducting silicon below, overcoming the surface states that prevented electricity from reaching the semiconducting layer.

为什么不需要画二氧化硅层SiO2 layer?

I haven’t draw the SiO2 layer here. Because this is our understanding that rest of the portion/area where no layer present, SiO2 is present.

为什么不需要画 P-Well ？

In an n-well process , the substrate is p -type (the wafer itself) and we use an n -well mask to build the n -well. We do not need a p -well mask because there are no p -wells in an n -well process—the n -channel transistors all sit in the substrate (the wafer)—but we often draw the p -well layer as though it existed.

MOS管的GATE门极的形成、绘制Poly layer（Polysilicon）

This Poly in the layout is same for GATE Poly and FIELD POLY. In Few cases there are different layers are defined for these type of layers which helps CAD tool to recognize.
除了为 NMOS 和 PMOS 晶体管形成栅极所需的两个区域外，多晶硅的剩余部分被剥离。形成GATE门极。
文章来源地址https://www.toymoban.com/news/detail-589544.html

Reference

1. CMOS Layout Design
2. 光刻机产业链——工业皇冠上的明珠：作者：狂暴小鳄鱼
3. /Lecture-4-Standard-Cell-Libraries
4. 光刻（Photolithography）介绍
5. What is Tapeout?
6. EUV for dummies
7. IC-Layout Design
8. Electric User’s Manual, version 9.07
9. Chap 4 - The Active and Poly Layers
10. CMOS Fabrication Process and MOSIS SCMOS Mask Layers

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