HDLbits---Circuits---Sequential Logic---Finite State Machines第四部分

这篇具有很好参考价值的文章主要介绍了HDLbits---Circuits---Sequential Logic---Finite State Machines第四部分。希望对大家有所帮助。如果存在错误或未考虑完全的地方,请大家不吝赐教,您也可以点击"举报违法"按钮提交疑问。

1.Exams/ece241 2013 q8

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
parameter start=2'b0,
    one=2'b01,
    two=2'b10,
    three=2'b11;
    reg[1:0] state,next_state;
    always@(posedge clk or negedge aresetn) begin
        if(aresetn==0)
            state<=start;
        else
            state<=next_state;
    end
    always@(*) begin
        case(state)
            start: 
                begin
                    if(x)
                        next_state<=one;
                    else
                        next_state<=start;
                end
             one: 
                begin
                    if(x)
                        next_state<=one;
                    else
                        next_state<=two;
                end
             two: 
                begin
                    if(x)
                        next_state<=three;
                    else
                        next_state<=start;
                end
             three: 
                begin
                    if(x)
                        next_state<=one;
                    else
                        next_state<=two;
                end
            default:
                begin
                    next_state<=start;
                end
            
        endcase
    end
    assign z=(next_state==three);
    
            
endmodule

2.Exams/ece241 2014 q5a

module top_module (
    input       clk,
    input       areset,
    input       x,
    output      z
); 
 
parameter  MSB    =  3'b001;
parameter  OUT_1  =  3'b010;
parameter  OUT_0  =  3'b100;
 
reg  [2:0]     state;
reg  [2:0]     next_state;
always @(posedge clk or posedge areset) begin
    if (areset) begin
        state <= MSB;
    end
    else begin
        state <= next_state;
    end
end
always @(*) begin
    next_state = state;
    case(state)
        MSB: begin
            if (x) begin
                next_state = OUT_1;
            end
            else begin
                next_state = MSB;
            end
        end
        OUT_1: begin
            if (x) begin
                next_state = OUT_0;
            end
            else begin
                next_state = OUT_1;
            end
        end
        OUT_0: begin
            if (~x) begin
                next_state = OUT_1;
            end
            else begin
                next_state = OUT_0;
            end
        end
        default: begin
            next_state = MSB;
        end
    endcase
end
assign z = (state==OUT_1);
 
endmodule

3.Exams/ece241 2014 q5b

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
reg state,next_state;
    parameter A=0,B=1;
    always@(posedge clk or posedge areset) begin
        if(areset)
            state<=A;
        else
            state<=next_state;
    end
    always@(*) begin
        case(state)
            A:
                begin
                    if(x==0)
                        next_state<=A;
                    else
                        next_state<=B;
                end
            B:
                begin
                        next_state<=B;
                end
            default:
                next_state<=A;
        endcase
    end
    assign z=(((state==A)&&x==1)||(state==B)&&(x==0));
                        
endmodule

4.Exams/2014 q3fsm

module top_module (
    input       clk,
    input       reset,   // Synchronous reset
    input       s,
    input       w,
    output      z
);
 
parameter  IDLE =  5'b00001;
parameter  A    =  5'b00010;
parameter  B    =  5'b00100;
parameter  C    =  5'b01000;
parameter  D    =  5'b10000;
reg  [4:0]    state;
reg  [4:0]    next_state;
reg  [10:0]   cnt;
always @(posedge clk) begin
    if (reset) begin
        state <= IDLE;
    end
    else begin
        state <= next_state;
    end
end
always @(*) begin
    case(state)
        IDLE: begin
            if (s) begin
                next_state = A;
            end
            else begin
                next_state = IDLE;
            end
        end
        A: begin
            next_state = B;
        end
        B: begin
            next_state = C;
        end
        C: begin
            next_state = D;
        end
        D: begin
            next_state = B;
        end
        default: begin
            next_state = IDLE;
        end
    endcase
end
always @(posedge clk) begin
    if (reset) begin
        cnt <= 'd0;
    end
    else begin
        case(next_state)
            IDLE: begin
                cnt <= 'd0;
            end
            A: begin
                cnt <= 'd0;
            end
            B: begin
                if (w) begin
                    cnt <= 'd1;
                end
                else begin
                    cnt <= 'd0;
                end
            end
            C: begin
                if (w) begin
                    cnt <= cnt + 'd1;
                end
                else begin
                    cnt <= cnt;
                end
            end
            D: begin
                if (w) begin
                    cnt <= cnt + 'd1;
                end
                else begin
                    cnt <= cnt;
                end
            end
        endcase
    end
end
 
assign z = (state==D && cnt=='d2);
endmodule

5.exams/2014_q3bfsm

module top_module (
input      clk,
input      reset,   // Synchronous reset
input      x,
output     z
);
parameter  A  =  3'b000;
parameter  B  =  3'b001;
parameter  C  =  3'b010;
parameter  D  =  3'b011;
parameter  E  =  3'b100;
reg  [2:0]  state;
reg  [2:0]  next_state;
always @(posedge clk) begin
if (reset) begin
state <= A;
end
else begin
state <= next_state;
end
end
always @(*) begin
next_state = state;
case(state)
A: begin
if (x) begin
next_state = B;
end
else begin
next_state = A;
end
end
B: begin
if (x) begin
next_state = E;
end
else begin
next_state = B;
end
end
C: begin
if (x) begin
next_state = B;
end
else begin
next_state = C;
end
end
D: begin
if (x) begin
next_state = C;
end
else begin
next_state = B;
end
end
E: begin
if (x) begin
next_state = E;
end
else begin
next_state = D;
end
end
default: begin
next_state = A;
end
endcase
end
assign z = (state==D) || (state==E);
endmodule

6.Exams/2014 q3c

module top_module (
input        clk,
input [2:0]  y,
input        x,
output       Y0,
output       z
);
parameter  A  =  3'b000;
parameter  B  =  3'b001;
parameter  C  =  3'b010;
parameter  D  =  3'b011;
parameter  E  =  3'b100;
reg  [2:0]   state;
always @(*) begin
case(y)
A: begin
if (x) begin
state = B;
end
else begin
state = A;
end
end
B: begin
if (x) begin
state = E;
end
else begin
state = B;
end
end
C: begin
if (x) begin
state = B;
end
else begin
state = C;
end
end
D: begin
if (x) begin
state = C;
end
else begin
state = B;
end
end
E: begin
if (x) begin
state = E;
end
else begin
state = D;
end
end
default: begin
state = A;
end
endcase
end
assign Y0 = state[0];
assign z = (y==D) || (y==E);
endmodule

7.Exams/m2014 q6b

module top_module (
input  [3:1]   y,
input          w,
output         Y2
);
parameter   A  =  3'b000;
parameter   B  =  3'b001;
parameter   C  =  3'b010;
parameter   D  =  3'b011;
parameter   E  =  3'b100;
parameter   F  =  3'b101;
reg  [3:1]   next_state;
always @(*) begin
case(y[3:1])
A: begin
if (w) begin
next_state = A;
end
else begin
next_state = B;
end
end
B: begin
if (w) begin
next_state = D;
end
else begin
next_state = C;
end
end
C: begin
if (w) begin
next_state = D;
end
else begin
next_state = E;
end
end
D: begin
if (w) begin
next_state = A;
end
else begin
next_state = F;
end
end
E: begin
if (w) begin
next_state = D;
end
else begin
next_state = E;
end
end
F: begin
if (w) begin
next_state = D;
end
else begin
next_state = C;
end
end
default: begin
next_state = A;
end
endcase
end
assign Y2 = next_state[2];
endmodule

8.m2014 q6c

module top_module (
input  [6:1]    y,
input           w,
output          Y2,
output          Y4
);
assign Y2 = ~w & y[1];
assign Y4 = (w&y[2]) | (w&y[3]) | (w&y[5]) | (w&y[6]);
endmodule

9.Exams/m2014 q6

module top_module (
input clk,
input reset,     // synchronous reset
input w,
output z);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg[2:0] state,next_state;
always@(posedge clk) begin
if(reset)
state<=A;
else
state<=next_state;
end
always@(*) begin
case(state)
A:
begin
if(w)
next_state<=A;
else
next_state<=B;
end
B:
begin
if(w)
next_state<=D;
else
next_state<=C;
end
C:
begin
if(w)
next_state<=D;
else
next_state<=E;
end
D:
begin
if(w)
next_state<=A;
else
next_state<=F;
end
E:
begin
if(w)
next_state<=D;
else
next_state<=E;
end
F:
begin
if(w)
next_state<=D;
else
next_state<=C;
end
default:
next_state<=A;
endcase
end
assign z=((state==E)||(state==F));
endmodule

10.Exams/2012 q2fsm

module top_module (
input clk,
input reset,     // synchronous reset
input w,
output z);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg[2:0] state,next_state;
always@(posedge clk) begin
if(reset)
state<=A;
else
state<=next_state;
end
always@(*) begin
case(state)
A:
begin
if(w)
next_state<=B;
else
next_state<=A;
end
B:
begin
if(w)
next_state<=C;
else
next_state<=D;
end
C:
begin
if(w)
next_state<=E;
else
next_state<=D;
end
D:
begin
if(w)
next_state<=F;
else
next_state<=A;
end
E:
begin
if(w)
next_state<=E;
else
next_state<=D;
end
F:
begin
if(w)
next_state<=C;
else
next_state<=D;
end
default:
next_state<=A;
endcase
end
assign z=((state==E)||(state==F));
endmodule

11.Exams/2012 q2b

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);
    parameter A = 3'b000,B = 3'b001,C = 3'b010,D = 3'b011,E = 3'b100,F = 3'b101;
    assign Y1 = w&y[A];
    assign Y3 = ~w&(y[B]|y[C]|y[E]|y[F]);
endmodule

12.Exams/2013 q2afsm

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
parameter A=0,B=1,C=2,D=3;
    reg[1:0] state,next_state;
    wire r1,r2,r3;
    assign r1=r[1],r2=r[2],r3=r[3];
    always@(posedge clk) begin
        if(resetn==0)
            state<=A;
        else
            state<=next_state;
    end
    always@(*) begin
        case(state)
            A: 
                begin
                if(r1==1)
                    next_state<=B;
                    else if(r2)
                    next_state<=C;
                    else if(r3)
                        next_state<=D;
                         else
                             next_state<=A;
            end
             B: 
                begin
                if(r1==1)
                    next_state<=B;
                else 
                    next_state<=A;
            end
             C: 
                begin
                    if(r2==1)
                    next_state<=C;
                else 
                    next_state<=A;
            end
             D: 
                begin
                    if(r3==1)
                    next_state<=D;
                else 
                    next_state<=A;
            end
        endcase
    end
    assign g[3]=(state==D);
    assign g[2]=(state==C);
    assign g[1]=(state==B);
    
                    
            
endmodule

13.exams/2013_q2bfsm

module top_module (
    input         clk,
    input         resetn,    // active-low synchronous reset
    input         x,
    input         y,
    output        f,
    output        g
);  
parameter   START  =  9'b000000001;
parameter   OUT_F  =  9'b000000010;
parameter   X_1    =  9'b000000100;
parameter   X_2    =  9'b000001000;
parameter   X_3    =  9'b000010000;
parameter   OUT_G  =  9'b000100000;
parameter   G_1    =  9'b001000000;
parameter   WAIT   =  9'b010000000;
parameter   G_0    =  9'b100000000;
reg  [8:0]   state;
reg  [8:0]   next_state;
always @(posedge clk) begin
    if (!resetn) begin
        state <= START;
    end
    else begin
        state <= next_state;
    end
end
always @(*) begin
    next_state = state;
    case(state)
        START: begin
            next_state = OUT_F;
        end
        OUT_F: begin
            next_state = X_1;
        end
        X_1: begin
            if (x) begin
                next_state = X_2;
            end
            else begin
                next_state = X_1;
            end
        end
        X_2: begin
            if (x) begin
                next_state = X_2;
            end
            else begin
                next_state = X_3;
            end
        end
        X_3: begin
            if (x) begin
                next_state = OUT_G;
            end
            else begin
                next_state = X_1;
            end
        end
        OUT_G: begin
            if (y) begin
                next_state = G_1;
            end
            else begin
                next_state = WAIT;
            end
        end
        WAIT: begin
            if (y) begin
                next_state = G_1;
            end
            else begin
                next_state = G_0;
            end
        end
        G_1: begin
            next_state = G_1;
        end
        G_0: begin
            next_state = G_0;
        end
        default: begin
            next_state = START;
        end
    endcase
end
assign f = state==OUT_F;
assign g = (state==OUT_G) | (state==G_1) | (state==WAIT);
endmodule

文章来源地址https://www.toymoban.com/news/detail-596576.html

到了这里,关于HDLbits---Circuits---Sequential Logic---Finite State Machines第四部分的文章就介绍完了。如果您还想了解更多内容,请在右上角搜索TOY模板网以前的文章或继续浏览下面的相关文章,希望大家以后多多支持TOY模板网!

本文来自互联网用户投稿,该文观点仅代表作者本人,不代表本站立场。本站仅提供信息存储空间服务,不拥有所有权,不承担相关法律责任。如若转载,请注明出处: 如若内容造成侵权/违法违规/事实不符,请点击违法举报进行投诉反馈,一经查实,立即删除!

领支付宝红包 赞助服务器费用

相关文章

  • 【HDLBits 刷题 5】Circuits(1)Combinational Logic

    目录 写在前面 Combinational Logic Basic Gates Wire GND NOR Another gate Two gates More logic gates 7420 chips Truth table Two bit equality Simple circuit A Simple circuit B Combine circuits A and B Ring or vibrate Thermostat 3 bit population count Gates and vectors Even longer vectors Multiplexers 2 to 1 mux 2 to 1 bus mux 9 to 1 mux 256 to 1 mux 256 t

    2024年02月02日
    浏览(38)
  • HDLBits刷题笔记7:Circuits.Combinational Logic.Karnaugh Map to Circuit

    3-variable 实现如下卡诺图,用sop和pos两种方式 化简: 4-variable 实现如下卡诺图,用sop和pos两种方式 化简: 4-variable 实现如下卡诺图 化简: 4-variable 实现如下卡诺图 此卡诺图不管是sop还是pos都没法化简,但不难看出,输入有奇数个1时,输出为1,所以是异或 minimum SOP and POS 一

    2024年02月11日
    浏览(35)
  • Circuits--Sequential--Registers_1

    1.4-bit shift register 2.Left/right rotator 3.Left / right arithmetic  4.5-bit LFSR

    2024年04月17日
    浏览(29)
  • Factorization Machines(论文笔记)

    样例一: 一个简单的例子,train是一个字典,先将train进行“one-hot” coding,然后输入相关特征向量,可以预测相关性。 样例二: 是基于真实的电影评分数据来训练。数据集点击下载即可。  样例三:是一个分类的样例 代码:pyFM/pyfm/pylibfm.py at master · coreylynch/pyFM (github.com)

    2024年02月16日
    浏览(30)
  • 有限差法(Finite Difference)求梯度和Hessian Matrix(海森矩阵)的python实现

    有限差方法求导, Finite Difference Approximations of Derivatives ,是数值计算中常用的求导方法。数学上也比较简单易用。本文主要针对的是向量值函数,也就是 f ( x ) : R n → R f(x):mathbb{R^n}rightarrow mathbb{R} f ( x ) : R n → R 当然,普通的标量值函数是向量值函数的一种特例。 本文采

    2024年02月03日
    浏览(40)
  • (表征学习论文阅读)FINITE SCALAR QUANTIZATION: VQ-VAE MADE SIMPLE

    向量量化(Vector Quantization)或称为矢量量化最早在1984年由Gray提出,主要应用于数据压缩、检索领域,具体的阐述可以参考我写的另一篇关于VQ算法的文章。随着基于神经网络的离散表征学习模型的兴起,VQ技术也开始重新被重视。它在图像、音频等表征学习中体现出了优秀的

    2024年04月26日
    浏览(28)
  • https://app.hackthebox.com/machines/Sau

    next time http://10.10.11.224:55555/haha35 altrail Documentation | Wiki | Issues | Log In Trails close Powered by Maltrail (v0.53) Hide threat Report false positive https://nvd.nist.gov/vuln/detail/CVE-2023-27163 https://github.com/spookier/Maltrail-v0.53-Exploit POC http://10.10.11.224:55555/haha35/ http://10.10.11.224:55555/haha352 curl ‘http://10.10.11.

    2024年02月14日
    浏览(54)
  • https://app.hackthebox.com/machines/Soccer

    https://app.hackthebox.com/machines/Soccer search exploit Download ZIP with latest version from master branch. Just copy the tinyfilemanager.php to your webspace - thats all 😃 You can also change the file name from “tinyfilemanager.php” to something else, you know what i meant for. Default username/password: admin/admin@123 and user/12345 . ⚠️ War

    2024年02月16日
    浏览(36)
  • https://app.hackthebox.com/machines/Squashed

    info collecting mount nfs files create user or: bash -i /dev/tcp/10.10.16.15/1337 01 browser 2.php create user ross su ross squash wget the .Xauthority Get the root’s desktop pic Wget the haha.xwd su root get the flag Ref:[https://www.jianshu.com/p/ef5201d9ffe7] (https://www.jianshu.com/p/ef5201d9ffe7) Squashed HTB Writeup https://www.jianshu.com/p/ef520

    2024年02月11日
    浏览(76)
  • swsim: A C++ Simulator for Digital Circuits

    Swsim is an open-source digital circuit simulator written in C++. It allows users to design, simulate and verify digital circuits using a simple and intuitive graphical interface. The project is available on GitCode. Swsim is a software tool that enables users to simulate the behavior of digital circuits. It supports various digital logic gates, flip-flops,

    2024年03月10日
    浏览(35)

觉得文章有用就打赏一下文章作者

支付宝扫一扫打赏

博客赞助

微信扫一扫打赏

请作者喝杯咖啡吧~博客赞助

支付宝扫一扫领取红包,优惠每天领

二维码1

领取红包

二维码2

领红包