报错
遇到想要保留的 Combinatorial Loop（组合逻辑换）如何解决 ？
- 严重警告：
[Synth 8-295] found timing loop.
- bit流报错
[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop.
This can create a race condition.
Timing analysis may not be accurate.
The preferred resolution is to modify the design to remove combinatorial logic loops.
If the loop is known and understood,
this DRC can be bypassed by acknowledging the condition and
setting the following XDC constraint on any one of the nets in the loop:
'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'.
One net in the loop is u0/TxValid_i_2_n_0.
Please evaluate your design.
The cells in the loop are: u0/TxValid_i_2.
- RTL图
确实存在输出又重新接到输入的环境
解决
在xdc文件中加入:
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets u0/TxValid_i_2_n_0]
用后面的提示替换<>中的内容文章来源：https://www.toymoban.com/news/detail-610411.html
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参考文章
- 点论 | 组合逻辑环 Combinational loop 知多少
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