verilog 八位并串转换代码
输入信号为8bit并行信号
该程序实现每8个时钟周期,便把收到的8bit并行信号拆解成串行信号并输出,等下8个时钟周期过后再转换下一个并行信号。文章来源:https://www.toymoban.com/news/detail-612814.html
并串转换代码
module b2c(input clk,
input rst_n,
input [7:0] data_i,
output reg data_o);
reg [2:0] cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_o <= 0;
cnt <= 3'b000;
end
else begin
if(cnt < 8)begin
data_o <= data_i[7-cnt];
cnt <= cnt + 1;
end
else begin
data_o <= data_i[7];
cnt <= 3'b001;
end
end
end
endmodule
时钟生成模块
`timescale 1ns / 1ps
module sim_s2f_cdc(
);
reg clk;
reg rst_n;
reg [7:0]data_i;
wire data_o;
initial begin
clk = 0;
forever
#2 clk = ~ clk;
end
initial begin
rst_n = 0;
data_i = 0;
#10
rst_n = 1;
#32
@(posedge clk)
data_i = 8'b10101010;
#32
@(posedge clk)
data_i = 8'b11101110;
#32
@(posedge clk)
data_i = 8'b10111011;
end
b2c inst_slow2fast(
.clk(clk),
.rst_n(rst_n),
.data_i(data_i),
.data_o(data_o)
);
endmodule
仿真图如下:
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