Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.
Build this circuit.
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module top_module (
input clk,
input x,
output z
);
wire d1,d2,d3,q1,q2,q3;
assign d1=x^q1;
assign d2=x&(~q2);
assign d3=x|(!q3);
always@(posedge clk) begin
q1<=d1;
q2<=d2;
q3<=d3;
end
assign z=~(q1|q2|q3);
endmodule
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