HDLBits_第1章_Verilog Language（已完结）-Toy模板网

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1. Verilog Language

1.1 Basics

1.1.1 Simple wire

1.1.2 Four wires

1.1.3 Inverter

1.1.4 AND gate

1.1.5 NOR gate

1.1.6 XNOR gate

1.1.7 Declaring wires

1.1.8 7458 chip

1.2 Vectors

1.2.1 Vectors

1.2.2 Vectors in more detail

1.2.3 Vector part select

1.2.4 Bitwise operators

1.2.5 Four-input gates

1.2.6 Vector concatenation operator

1.2.7 Vector reversal

1.2.8 Replication operator

1.2.9 More replication

1.3 Modules:Hierarchy

1.3.1 Modules

1.3.2 Connecting ports by name

1.3.3 Connecting ports by name

1.3.4 Three modules

1.3.5 Modules and vectors

1.3.6 Adder 1 Module add

1.3.7 Adder 2 - Module fadd

1.3.8 Carry-select adder

1.3.9 Adder-subtractor

1.4 Procedures

1.4.1 Always blocks(combination)

1.4.2 Always blocks(clocked)

1.4.3 If statement

1.4.4 If statement latches

1.4.5 Case statement

1.4.6 Priority encoder

1.4.7 Priority encoder with casez

1.4.8 Avoiding latches

1.5 More Verilog Features

1.5.1 Conditional ternary operator

1.5.2 Reduction operators

1.5.3 Reduction: Even wider gates

1.5.4 Combinational for-loop:Vector reversal 2

1.5.5 Combinational for-loop:255bit population count

1.5.6 Generate for-loop:100bit binary adder2

1.5.7 Generate for-loop:100-Digit BCD adder

1. Verilog Language

1.1 Basics

1.1.1 Simple wire

Wire线网型

Create a module with one input and one output that behaves like a wire.

创建一个单输入单输出的模块，该行为类似于线连

Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog "continuous assignment" (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is "continuous" because the assignment continues all the time even if the right side's value changes. A continuous assignment is not a one-time event.

与物理连线不同，Verilog中的连线（或者信号）具有方向性。这意味着信息只向一个方向传输，从源端口流向接收端口（源也经常被成为将值驱动到线路上的驱动程序）。在Verilog的”连续赋值“中（assign left_side = right_side），右侧信号的值会被赋值到左侧信号的wire上。赋值是”连续的“，因为赋值一直在发生，只要右侧的值改变左侧是值也会立即改变。持续赋值不是一个时间的事件。

The ports on a module also have a direction (usually input or output). An input port is driven by something from outside the module, while an output port drives something outside. When viewed from inside the module, an input port is a driver or source, while an output port is a sink.

模块上的端口也有方向性（通常为输入端或输出端）。输入端口驱通过模块外部驱动，输出端口驱动其他模块。从模块内部看，输入端口是驱动信号或者源，而输出端口是接收端口

The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. The module and port declarations create the black portions of the circuit. Your task is to create a wire (in green) by adding an assign statement to connect in to out. The parts outside the box are not your concern, but you should know that your circuit is tested by connecting signals from our test harness to the ports on your top_module.

下图说明了电路的每个部分如何对应于Verilog代码的每个比特位。模块和端口声明创建了电路图中的黑色部分。您的任务是通过添加一个assign语句来连接输入in和输出out。黑色方框外部的部分不是你所关心的内容，单你应该知道，你的电路时通过将我们的测试线束的信号连接到top_module上的端口来进行测试的。

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In addition to continuous assignments, Verilog has three other assignment types that are used in procedural blocks, two of which are synthesizable. We won't be using them until we start using procedural blocks.

除了连续赋值，Verilog还有三种其他的用于程序块的赋值类型，其中两种是可综合的。我们在开始使用程序块之前，先不使用他们。

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1.1.2 Four wires

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

创建一个具有3输入4输出的模块，该模块功能实现下述线网连接：

a -> w
b -> x
b -> y
c -> z

The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. From outside the module, there are three input ports and four output ports.

下图说明电路的每个部分对应Verilog的每个比特位。从模块外部看，有3个输入端口和4个输出端口。

When you have multiple assign statements, the order in which they appear in the code does not matter. Unlike a programming language, assign statements ("continuous assignments") describe connections between things, not the action of copying a value from one thing to another.

当你有多个赋值语句时，他们出现在代码中的顺序不重要。与编程语言不同，Verilog的赋值语句（连续赋值语句）描述硬件之间的连接，而不是将一个变量值复制到另一个变量的操作。

One potential source of confusion that should perhaps be clarified now: The green arrows here represent connections between wires, but are not wires in themselves. The module itself already has 7 wires declared (named a, b, c, w, x, y, and z). This is because input and output declarations actually declare a wire unless otherwise specified. Writing input wire a is the same as input a. Thus, the assign statements are not creating wires, they are creating the connections between the 7 wires that already exist.

现在应该澄清的一个容易混淆的潜在的数据源：这里的绿色箭头代表wire之间的连接关系，但实际并不是导线。模块本身已经声明了7个wire的连接（a,b,c,w,x,y,z），这是因为在input和output声明已经声明是wire，若有单独声明则另外讨论。代码中，input wire a和input a是一样的。因此，assign语句不是在创建连线wires，而是在创建7个已经存在的wires之间的联系。

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Expected solution length: Around 4 lines.

期望解决方案长度：4行。

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1.1.3 Inverter

Create a module that implements a NOT gate.

创建一个实现NOT门（非门）的模块。

This circuit is similar to wire, but with a slight difference. When making the connection from the wire in to the wire out we're going to implement an inverter (or "NOT-gate") instead of a plain wire.

这个电路类似与wire，但是有细微区别。当从线in连接到线out时，我们期望实现一个逆变器（非门），而不是不同的wire连接

Use an assign statement. The assign statement will continuously drive the inverse of in onto wire out.

使用赋值语句，赋值语句将连续驱动in的逆赋值给out

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Expected solution length: Around 1 line.

期待解决方案长度：1行

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1.1.4 AND gate

Create a module that implements an AND gate.

创建一个实现AND gate（与门）的模块。

This circuit now has three wires (a, b, and out). Wires a and b already have values driven onto them by the input ports. But wire out currently is not driven by anything. Write an assign statement that drives out with the AND of signals a and b.

这个电路有三条线（a,b和out）。wire a和b已经有输入端口驱动其数值。但是wire out目前不受任何驱动。写一个赋值语句，驱动out输出a和b的与计算。

Note that this circuit is very similar to the NOT gate, just with one more input. If it sounds different, it's because I've started describing signals as being driven (has a known value determined by something attached to it) or not driven by something. Input wires are driven by something outside the module. assign statements will drive a logic level onto a wire. As you might expect, a wire cannot have more than one driver (what is its logic level if there is?), and a wire that has no drivers will have an undefined value (often treated as 0 when synthesizing hardware).

注意，这个电路与NOT gate（非门）非常相似，只是多了一个输入。如果听起来不一样，是因为，我们已经开始描述信号驱动（有附加到他的某个东西决定的已知值），而不是通过某种东西驱动。输入线由模块外所驱动。赋值语句通过逻辑级驱动到线wire上。正如您说期望的，一个wire不能有多个驱动程序（如果有多个驱动，那驱动的逻辑是什么呢？），没有驱动程序的线路加ing有一个未定义的值（在综合硬件时通常被视为0）。

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Expected solution length: Around 1 line.

期望解决方案长度：1行

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1.1.5 NOR gate

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

创建一个实现NOR gate（或非门）的模块。或非门的输出是或门的倒置。在Verilog语言中，或非门函数需要两个操作符。

An assign statement drives a wire (or "net", as it's more formally called) with a value. This value can be as complex a function as you want, as long as it's a combinational (i.e., memory-less, with no hidden state) function. An assign statement is a continuous assignment because the output is "recomputed" whenever any of its inputs change, forever, much like a simple logic gate.

赋值语句驱动带有值的线（更正式的叫法是：网）。这个值可以是你想要的任意复杂的函数，只要他是一个组合函数（即无内存，无隐藏状态）。赋值语句是连续的赋值，因为只要输入input改变，输出output就会被重新计算，就像一个简单的逻辑门一样。

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