1:修改E203 RTL
在原top再增加一个soc.v
修改点
1）时钟
e203_soc_top需要两个时钟，一个为16MHz，一个为32.768KHz。由于领航者ZYNQ FPGA开发板只有一个50MHz的输入晶振时钟。因此，要实现一个类似SOC中PLL模块的分频功能，为了简单直接用于fpga mmcm ip产生一个16M，再通过16M分频得到32.768KHz时钟。
2、关于GPIO
由于领航者开发板IO足够，不对GPIO进行删减。但是要注意，GPIOA[16]、GPIOA[17]是E203默认的UART0的PAD，这两个PAD需要连接到使用的串口引脚。或者按需要换成自己需要的管脚
以领航者ZYNQ开发板为例：
其他GPIO保留，后面在隐射到增加的IP 端口上，先配置为其他空闲的管脚
3、QSPI与ROM启动
由于领航者开发板没有多余的flash，因此芯片启动只能选择ROM启动。
4、power wakeup及指示
由于还要LED及按键空闲，先使用上（该PAD不需要也可以删除，wakeup 信号需要tie 1’b1 ）
5、修改结果可综合：
期间遇到两个问题：
1）vavido include无法识别。 Setting > general > Verilog options > 增加文件路径
2）sim top 文件增加define值无效，暂时未解决。（先再define文件中加入这两个define）
修改后的soc.v
//-----------------------------------------------------------------------------------------
// Project Name : soc
// Module Name : soc.v
// Revision : v1.0
// Conpany :
// Editor : Jevon
// Email : jevonhjw@163.com
// create Date : 2023-01-14
// Descriptions : SOC project with E203 RISCV CPU
//-----------------------------------------------------------------------------------------
`timescale 1ns/10ps
module soc (
input wire clk_sys , //50MHz
input wire rstn_sys , //low active
inout wire mcu_tdo ,
inout wire mcu_tck ,
inout wire mcu_tdi ,
inout wire mcu_tms ,
inout wire [31:0] GPIOA , //GPIOA00~GPIOA31
inout wire [31:0] GPIOB , //GPIOB00~GPIOB31
input wire pad_wakeup , //low power default
output wire pad_power_led , //to LED
output wire pad_rst_led //to LED
);
//--------------------------------------------------------------------------
//define and parameter
//--------------------------------------------------------------------------
//signals
wire clk_16M ;
wire CLK32768KHZ ;
wire ck_rst ;
wire dut_io_pads_jtag_TCK_i_ival ;
wire dut_io_pads_jtag_TMS_i_ival ;
wire dut_io_pads_jtag_TDI_i_ival ;
wire dut_io_pads_jtag_TDO_o_oval ;
wire dut_io_pads_jtag_TDO_o_oe ;
wire dut_io_pads_bootrom_n_i_ival ;
wire dut_io_pads_aon_pmu_dwakeup_n_i_ival ;
wire dut_io_pads_aon_pmu_vddpaden_o_oval ;
wire dut_io_pads_aon_pmu_padrst_o_oval ;
//--------------------------------------------------------------------------
//PLL logic
wire clk_16m ;
wire locked ;
reg sync_d0 ;
reg sync_d1 ;
wire rstn_tmp ;
wire rstn ;
reg [11:0] div_cnt ;
wire [11:0] div_cnt_num ;
wire div_cnt_end ;
reg div_reg ;
clk_wiz_0 u_clk_wiz_0(
.clk_out1(clk_16m ), // output clk_out1
.resetn (rstn_sys ), // input reset
.locked (locked ), // output locked
.clk_in1 (clk_sys ) // input clk_in1
);
assign rstn_tmp = locked & rstn_sys ;
always @(posedge clk_16m or negedge rstn_tmp)begin
if(!rstn_tmp) begin sync_d0 <= #1 1'h0 ;
sync_d1 <= #1 1'h0 ;
end else begin sync_d0 <= #1 1'h1 ;
sync_d1 <= #1 sync_d0 ;
end
end
assign rstn = sync_d1 ; //sync reset logic
assign div_cnt_num = 12'd2440 ;
assign div_cnt_end = div_cnt == div_cnt_num ;
always @(posedge clk_16m or negedge rstn)begin
if(!rstn) div_cnt <= #1 12'h0 ;
else if(div_cnt_end) div_cnt <= #1 12'h0 ;
else div_cnt <= #1 div_cnt + 1'b1 ;
end
always @(posedge clk_16m or negedge rstn)begin
if(!rstn) div_reg <= #1 1'h0 ;
else if(div_cnt_end) div_reg <= #1 !div_reg ;
end
//--------------------------------------------------------------------------
//pinmux for FPGA
//JTAG
wire mcu_tck_i ;
wire mcu_tms_i ;
wire mcu_tdi_i ;
wire mcu_tdo_i ;
wire mcu_tdo_o ;
wire mcu_tdo_oen ;
PULLUP pullup_TCK (.O(mcu_tck));
PULLUP pullup_TMS (.O(mcu_tms));
PULLUP pullup_TDI (.O(mcu_tdi));
IOBUF IOBUF_jtag_tck ( .O(mcu_tck_i),.IO(mcu_tck),.I(1'b0 ),.T(1'b1 )); //T low active
IOBUF IOBUF_jtag_tms ( .O(mcu_tms_i),.IO(mcu_tms),.I(1'b0 ),.T(1'b1 )); //T low active
IOBUF IOBUF_jtag_tdi ( .O(mcu_tdi_i),.IO(mcu_tdi),.I(1'b0 ),.T(1'b1 )); //T low active
IOBUF IOBUF_jtag_tdo ( .O(mcu_tdo_i),.IO(mcu_tdo),.I(mcu_tdo_o),.T(mcu_tdo_oen)); //T low active
assign dut_io_pads_jtag_TCK_i_ival = mcu_tck_i ;
assign dut_io_pads_jtag_TMS_i_ival = mcu_tms_i ;
assign dut_io_pads_jtag_TDI_i_ival = mcu_tdi_i ;
assign mcu_tdo_o = dut_io_pads_jtag_TDO_o_oval ;
assign mcu_tdo_oen = ~dut_io_pads_jtag_TDO_o_oe ;
wire [31:0] gpioa_i ;
wire [31:0] gpioa_o ;
wire [31:0] gpioa_oe ;
wire [31:0] gpiob_i ;
wire [31:0] gpiob_o ;
wire [31:0] gpiob_oe ;
IOBUF IOBUF_gpioa[31:0] ( .O(gpioa_i),.IO(GPIOA),.I(gpioa_o ),.T(!gpioa_oe)); //T low active 31
IOBUF IOBUF_gpiob[31:0] ( .O(gpiob_i),.IO(GPIOB),.I(gpiob_o ),.T(!gpiob_oe)); //T low active 31
//--------------------------------------------------------------------------
//instance
assign clk_16M = clk_16m ;
assign CLK32768KHZ = div_reg ;
assign ck_rst = rstn ;
// 0:internal ROM (0x0000_1000)~0x0000_1FFFF
// 1:from QSPI_FLASH (0x2000_0000)
assign dut_io_pads_bootrom_n_i_ival = 1'b0 ;
assign dut_io_pads_aon_pmu_dwakeup_n_i_ival = pad_wakeup ;
assign pad_power_led = dut_io_pads_aon_pmu_vddpaden_o_oval ;
assign pad_rst_led = dut_io_pads_aon_pmu_padrst_o_oval ;
e203_soc_top u_core
(
.hfextclk(clk_16M),
.hfxoscen(),
.lfextclk(CLK32768KHZ),
.lfxoscen(),
// Note: this is the real SoC top AON domain slow clock
.io_pads_jtag_TCK_i_ival(dut_io_pads_jtag_TCK_i_ival),
.io_pads_jtag_TMS_i_ival(dut_io_pads_jtag_TMS_i_ival),
.io_pads_jtag_TDI_i_ival(dut_io_pads_jtag_TDI_i_ival),
.io_pads_jtag_TDO_o_oval(dut_io_pads_jtag_TDO_o_oval),
.io_pads_jtag_TDO_o_oe (dut_io_pads_jtag_TDO_o_oe),
.io_pads_gpioA_i_ival(gpioa_i),
.io_pads_gpioA_o_oval(gpioa_o),
.io_pads_gpioA_o_oe (gpioa_oe),
.io_pads_gpioB_i_ival(gpiob_i),
.io_pads_gpioB_o_oval(gpiob_o),
.io_pads_gpioB_o_oe (gpiob_oe),
.io_pads_qspi0_sck_o_oval ( ), //no flash
.io_pads_qspi0_cs_0_o_oval( ),
.io_pads_qspi0_dq_0_i_ival(1'b0 ),
.io_pads_qspi0_dq_0_o_oval( ),
.io_pads_qspi0_dq_0_o_oe ( ),
.io_pads_qspi0_dq_1_i_ival(1'b0 ),
.io_pads_qspi0_dq_1_o_oval( ),
.io_pads_qspi0_dq_1_o_oe ( ),
.io_pads_qspi0_dq_2_i_ival(1'b0 ),
.io_pads_qspi0_dq_2_o_oval( ),
.io_pads_qspi0_dq_2_o_oe ( ),
.io_pads_qspi0_dq_3_i_ival(1'b0 ),
.io_pads_qspi0_dq_3_o_oval( ),
.io_pads_qspi0_dq_3_o_oe ( ),
// Note: this is the real SoC top level reset signal
.io_pads_aon_erst_n_i_ival (ck_rst ), //system reset low active
.io_pads_aon_pmu_dwakeup_n_i_ival (dut_io_pads_aon_pmu_dwakeup_n_i_ival ),
.io_pads_aon_pmu_vddpaden_o_oval (dut_io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_aon_pmu_padrst_o_oval (dut_io_pads_aon_pmu_padrst_o_oval ),
.io_pads_bootrom_n_i_ival (dut_io_pads_bootrom_n_i_ival ),
.io_pads_dbgmode0_n_i_ival (1'b1 ),
.io_pads_dbgmode1_n_i_ival (1'b1 ),
.io_pads_dbgmode2_n_i_ival (1'b1 )
);
//--------------------------------------------------------------------------
endmodule
SDC约束
注：32.768KHz时钟点div_reg寄存器未约束，由FPGA自行判断。
set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports clk_sys]
create_clock -add -name clk_50m -period 20.00 -waveform {0 5} [get_ports {clk_sys}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IOBUF_jtag_tck/O]
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports rstn_sys]
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports pad_wakeup]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports pad_power_led]
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33} [get_ports pad_rst_led]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports mcu_tck]
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports mcu_tms]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports mcu_tdo]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports mcu_tdi]
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {GPIOA[31]}]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {GPIOA[30]}]
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {GPIOA[29]}]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports {GPIOA[28]}]
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {GPIOA[27]}]
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {GPIOA[26]}]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {GPIOA[25]}]
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {GPIOA[24]}]
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports {GPIOA[23]}]
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {GPIOA[22]}]
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {GPIOA[21]}]
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {GPIOA[20]}]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {GPIOA[19]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {GPIOA[18]}]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {GPIOA[17]}]
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {GPIOA[16]}]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {GPIOA[15]}]
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33} [get_ports {GPIOA[14]}]
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {GPIOA[13]}]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {GPIOA[12]}]
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {GPIOA[11]}]
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {GPIOA[10]}]
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports {GPIOA[9]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {GPIOA[8]}]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {GPIOA[7]}]
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports {GPIOA[6]}]
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {GPIOA[5]}]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {GPIOA[4]}]
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS33} [get_ports {GPIOA[3]}]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports {GPIOA[2]}]
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {GPIOA[1]}]
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {GPIOA[0]}]
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {GPIOB[31]}]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports {GPIOB[30]}]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS33} [get_ports {GPIOB[29]}]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {GPIOB[28]}]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {GPIOB[27]}]
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports {GPIOB[26]}]
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {GPIOB[25]}]
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports {GPIOB[24]}]
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {GPIOB[23]}]
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {GPIOB[22]}]
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports {GPIOB[21]}]
set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {GPIOB[20]}]
set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {GPIOB[19]}]
set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports {GPIOB[18]}]
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports {GPIOB[17]}]
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {GPIOB[16]}]
set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {GPIOB[15]}]
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {GPIOB[14]}]
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {GPIOB[13]}]
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {GPIOB[12]}]
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {GPIOB[11]}]
set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {GPIOB[10]}]
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {GPIOB[9]}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {GPIOB[8]}]
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {GPIOB[7]}]
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {GPIOB[6]}]
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {GPIOB[5]}]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {GPIOB[4]}]
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {GPIOB[3]}]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {GPIOB[2]}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports {GPIOB[1]}]
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {GPIOB[0]}]
参考：
1）https://www.bilibili.com/video/BV1ia411U76P
2）https://blog.csdn.net/qq_44447544/article/details/123281503文章来源：https://www.toymoban.com/news/detail-736626.html
上板验证
由于RISCV调试器还没购买，只能等年后再更新上板验证…文章来源地址https://www.toymoban.com/news/detail-736626.html
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