「Verilog学习笔记」使用握手信号实现跨时钟域数据传输

专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

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`timescale 1ns/1ns
module data_driver(
	input clk_a,
	input rst_n,
	input data_ack,
	output reg [3:0]data,
	output reg data_req
	);

	reg data_ack_reg_1, data_ack_reg_2 ; 
	reg [9:0] cnt ; 

	always @ (posedge clk_a or negedge rst_n) begin 
		if (~rst_n) begin 
			data_ack_reg_1 <= 0 ;
			data_ack_reg_2 <= 0 ; 
		end
		else begin 
			data_ack_reg_1 <= data_ack ; 
			data_ack_reg_2 <= data_ack_reg_1 ;
		end
	end

	always @ (posedge clk_a or negedge rst_n) begin 
		if (~rst_n) data <= 0 ; 
		else if (data_ack_reg_1 && !data_ack_reg_2) data <= data + 1 ; 
		else data <= data ; 
	end

	always @ (posedge clk_a or negedge rst_n) begin 
		if (~rst_n) cnt <= 0 ; 
		else if (data_ack_reg_1 && !data_ack_reg_2) cnt <= 0 ; 
		else if (data_req) cnt <= cnt ; 
		else cnt <= cnt + 1 ;
	end

	always @ (posedge clk_a or negedge rst_n) begin 
		if (~rst_n) data_req <= 0 ; 
		else if (cnt == 4) data_req <= 1 ; 
		else if (data_ack_reg_1 && !data_ack_reg_2) data_req <= 0 ; 
		else data_req <= data_req ; 
	end

endmodule

module data_receiver (
	input clk_b, 
	input rst_n,
	input data_req,
	input [3:0] data,
	output reg data_ack
);
	reg [3:0] data_in_reg ; 
	reg data_req_reg_1, data_req_reg_2 ; 
	always @ (posedge clk_b or negedge rst_n) begin 
		if (~rst_n) begin 
			data_req_reg_1 <= 0 ;
			data_req_reg_2 <= 0 ; 
		end
		else begin
			data_req_reg_1 <= data_req ; 
			data_req_reg_2 <= data_req_reg_1 ; 
		end
	end

	always @ (posedge clk_b or negedge rst_n) begin 
		if (~rst_n) data_ack <= 0 ;
		else if (data_req_reg_1) data_ack <= 1 ; 
		else data_ack <= 0 ;
	end

	always @ (posedge clk_b or negedge rst_n) begin 
		if (~rst_n) data_in_reg <= 0 ; 
		else if (data_req_reg_1 && !data_req_reg_2) data_in_reg <= data ; 
		else data_in_reg <= data_in_reg ;
	end

endmodule

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