![[place 30-574] poor placement for routing between an io pin and bufg. if thi,XILINX FPGA 开发经验专栏,嵌入式硬件,FPGA,XILINX](https://imgs.yssmx.com/Uploads/2024/01/781395-1.png)
问题描述
最近利用手头的开发板作UDP通信的设计。准备生成比特流时，出现这个错误：
![[place 30-574] poor placement for routing between an io pin and bufg. if thi,XILINX FPGA 开发经验专栏,嵌入式硬件,FPGA,XILINX](https://imgs.yssmx.com/Uploads/2024/01/781395-2.png)
具体信息：
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets I_PHY_RX_CLK_IBUF] >I_PHY_RX_CLK_IBUF_inst (IBUF.O) is locked to IOB_X0Y42
and I_PHY_RX_CLK_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
翻译：
IO引脚和BUFG之间的布线放置不当。如果此次优化条件可用于此设计，则可以使用.xdc文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为警告。但是，强烈不鼓励使用此覆盖。这些示例可以直接在.xdc文件中使用，以覆盖此时钟规则。
<set_property CLOCK_DEDICATED_ROUTE FALSE[get_nets I_PHY_RX_CLK_IBUF]>
I_PHY_RX_CLK_IBUF_inst（IBUF.O）锁定到IOB_X0Y42，I_PHY_RX_CLK_IBUF_BUFG_inst（BUFG.I）由BUFGTRL_X0Y1上的时钟放置器临时放置
电路原理图
此时钟由外部的网络PHY芯片输入，且未经过专门的时钟IO口，走的是普通IO引脚，普通IO引脚附近没有时钟资源，比如全局缓冲器 BUFG等，所以在布局时就出现问题。
![[place 30-574] poor placement for routing between an io pin and bufg. if thi,XILINX FPGA 开发经验专栏,嵌入式硬件,FPGA,XILINX](https://imgs.yssmx.com/Uploads/2024/01/781395-3.png)
解决
按照错误中给出的方法，可以在XDC里面对该时钟信号增加如下约束，将此错误降低为警告。
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets I_PHY_RX_CLK]可以正常生成比特流了：
![[place 30-574] poor placement for routing between an io pin and bufg. if thi,XILINX FPGA 开发经验专栏,嵌入式硬件,FPGA,XILINX](https://imgs.yssmx.com/Uploads/2024/01/781395-4.png)
查看警告信息，此处的错误已经变成警告了：
![[place 30-574] poor placement for routing between an io pin and bufg. if thi,XILINX FPGA 开发经验专栏,嵌入式硬件,FPGA,XILINX](https://imgs.yssmx.com/Uploads/2024/01/781395-5.png)
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