基于xilinx 7系列fpga的xdc代码，获取fpga内部温度、各电压值-Toy模板网

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一、注意事项

1、参考文档：UG480(7Series_XADC)和PG091(XADC_Wizard)；
2、一个FPGA内部只有一个ADC模块，当我们使用了MIG控制器时，在生成MIG的过程中要disable XADC，否则会产生冲突；
3、内部的ADCCLK最大时钟速率为26MHz，程序中默认ADCCLK=DCLK/4；
4、ADC的最大转换速率为1MSPS。

二、温度和电压值的计算：

1、Temp=[(MEASURED_TEMP[15:4]*503.975)/4096] – 273.15;
2、Vccint=(MEASURED_VCCINT[15:4]*3)/4096;
3、Vccaux,Vccbram的电压转换方式和Vccint一样；

三、例化接口

DCLK通常为50M或100MHz，复位信号高有效，其VAUXP，VAUXN，VP，VN四个输入信号可直接给0，例化的接口如下：

XADC_7series_Measure XADC_7series_Measure_inst(
        .DCLK               (clk_100m       ), // Clock input for DRP
        .RESET              (reset_H        ),//active high
        .VAUXP              ('d0), 
        .VAUXN              ('d0), // Auxiliary analog channel inputs
        .VP                 ('b0), 
        .VN                 ('b0),// Dedicated and Hardwired Analog Input Pair
        .MEASURED_TEMP      (fpga_temp      ), 
        .MEASURED_VCCINT    (fpga_vccint    ),
        .MEASURED_VCCAUX    (fpga_vccaux    ), 
        .MEASURED_VCCBRAM   (),
        .MEASURED_AUX0      (),
        .MEASURED_AUX1      (),
        .MEASURED_AUX2      (), 
        .MEASURED_AUX3      (),
        .ALM                (),
        .CHANNEL            (),
        .OT                 (),
        .XADC_EOC           (),
        .XADC_EOS           ()
    );

四、代码

module XADC_7series_Measure (
input DCLK, // Clock input for DRP
input RESET,
input [3:0] VAUXP, VAUXN, // Auxiliary analog channel inputs
input VP, VN,// Dedicated and Hardwired Analog Input Pair
output reg [15:0] MEASURED_TEMP, MEASURED_VCCINT,
output reg [15:0] MEASURED_VCCAUX, MEASURED_VCCBRAM,
output reg [15:0] MEASURED_AUX0, MEASURED_AUX1,
output reg [15:0] MEASURED_AUX2, MEASURED_AUX3,
output wire [7:0] ALM,
output wire [4:0] CHANNEL,
output wire OT
);
wire busy;
wire [5:0] channel;
wire drdy;
reg [6:0] daddr;
reg [15:0] di_drp;
wire [15:0] do_drp;
wire [15:0] vauxp_active;
wire [15:0] vauxn_active;
reg [1:0] den_reg;
reg [1:0] dwe_reg;
parameter init_read = 8'h00,
read_waitdrdy = 8'h01,
write_waitdrdy = 8'h03,
read_reg00 = 8'h04,
reg00_waitdrdy = 8'h05,
read_reg01 = 8'h06,
reg01_waitdrdy = 8'h07,
read_reg02 = 8'h08,
reg02_waitdrdy = 8'h09,
read_reg06 = 8'h0a,
reg06_waitdrdy = 8'h0b,
read_reg10 = 8'h0c,
reg10_waitdrdy = 8'h0d,
read_reg11 = 8'h0e,
reg11_waitdrdy = 8'h0f,
read_reg12 = 8'h10,
reg12_waitdrdy = 8'h11,
read_reg13 = 8'h12,
reg13_waitdrdy = 8'h13;

reg [7:0] state = init_read;
wire    eoc;
wire    eos;

always @(posedge DCLK)
if (RESET) begin
state <= init_read;
den_reg <= 2'h0;
dwe_reg <= 2'h0;
di_drp <= 16'h0000;
end
else
case (state)
init_read : begin
daddr = 7'h40;
den_reg = 2'h2; // performing read
if (busy == 0 ) state <= read_waitdrdy;
end
read_waitdrdy :
if (drdy ==1) begin
di_drp = do_drp & 16'h03_FF; //Clearing AVG bits for Configreg0
daddr = 7'h40;
den_reg = 2'h2;
dwe_reg = 2'h2; // performing write
state = write_waitdrdy;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
write_waitdrdy :
if (drdy ==1) begin
state = read_reg00;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg00 : begin
daddr = 7'h00;
den_reg = 2'h2; // performing read
if (eos == 1) state <=reg00_waitdrdy;
end
reg00_waitdrdy :
if (drdy ==1) begin
MEASURED_TEMP = do_drp;
state <=read_reg01;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg01 : begin
daddr = 7'h01;
den_reg = 2'h2; // performing read
state <=reg01_waitdrdy;
end
reg01_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCINT = do_drp;
state <=read_reg02;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg02 : begin
daddr = 7'h02;
den_reg = 2'h2; // performing read
state <=reg02_waitdrdy;
end
reg02_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCAUX = do_drp;
state <=read_reg06;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg06 : begin
daddr = 7'h06;
den_reg = 2'h2; // performing read
state <=reg06_waitdrdy;
end
reg06_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCBRAM = do_drp;
state <= read_reg10;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg10 : begin
daddr = 7'h10;
den_reg = 2'h2; // performing read
state <= reg10_waitdrdy;
end
reg10_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX0 = do_drp;
state <= read_reg11;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg11 : begin
daddr = 7'h11;
den_reg = 2'h2; // performing read
state <= reg11_waitdrdy;
end
reg11_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX1 = do_drp;
state <= read_reg12;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg12 : begin
daddr = 7'h12;
den_reg = 2'h2; // performing read
state <= reg12_waitdrdy;
end
reg12_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX2= do_drp;
state <= read_reg13;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg13 : begin
daddr = 7'h13;
den_reg = 2'h2; // performing read
state <= reg13_waitdrdy;
end
reg13_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX3= do_drp;
state <=read_reg00;
daddr = 7'h00;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
endcase

XADC #(     // Initializing the XADC Control Registers
.INIT_40(16'h9000),// averaging of 16 selected for external channels
.INIT_41(16'h2ef0),// Continuous Seq Mode, Disable unused ALMs, Enable calibration
.INIT_42(16'h0400),// Set DCLK divides
.INIT_48(16'h4701),// CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration
.INIT_49(16'h000f),// CHSEL2 - enable aux analog channels 0 - 3
.INIT_4A(16'h0000),// SEQAVG1 disabled
.INIT_4B(16'h0000),// SEQAVG2 disabled
.INIT_4C(16'h0000),// SEQINMODE0
.INIT_4D(16'h0000),// SEQINMODE1
.INIT_4E(16'h0000),// SEQACQ0
.INIT_4F(16'h0000),// SEQACQ1
.INIT_50(16'hb5eb),// Temp upper alarm trigger 85°C
.INIT_51(16'h599a),// Vccint upper alarm limit 1.05V
.INIT_52(16'hA148),// Vccaux upper alarm limit 1.89V
.INIT_53(16'h0000),// OT upper alarm limit 125°C using automatic shutdown - see Thermal
.INIT_54(16'ha939),// Temp lower alarm reset 60°C
.INIT_55(16'h5112),// Vccint lower alarm limit 0.95V
.INIT_56(16'h91Ed),// Vccaux lower alarm limit 1.71V
.INIT_57(16'hae4f),// OT lower alarm reset 70°C - see Thermal Management
.INIT_58(16'h599a),// VCCBRAM upper alarm limit 1.05V
)
XADC_INST (// Connect up instance IO. See UG580 for port descriptions
.CONVST (1'b0),// not used
.CONVSTCLK (1'b0), // not used
.DADDR (daddr),
.DCLK (DCLK),
.DEN (den_reg[0]),
.DI (di_drp),
.DWE (dwe_reg[0]),
.RESET (RESET),
.VAUXN (vauxn_active ),
.VAUXP (vauxp_active ),
.ALM (ALM),
.BUSY (busy),
.CHANNEL(CHANNEL),
.DO (do_drp),
.DRDY (drdy),
.EOC (eoc),
.EOS (eos),
.JTAGBUSY (),// not used
.JTAGLOCKED (),// not used
.JTAGMODIFIED (),// not used
.OT (OT),
.MUXADDR (),// not used
.VP (VP),
.VN (VN)
);