Vivado Error问题之[DRC NSTD-1][DRC UCIO-1] FPGA管脚约束问题导致生成bit时报错，如何在不重新Implentation情况下生成bit？-Toy模板网

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一、报错信息如下：

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 9 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.
This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SYS_CLK.

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 9 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SYS_CLK.

二、问题原因

由于在约束中忘记对SYS_CLK的管脚进行约束，经过了长时间的综合和实现后，最后的Generate Bitstream报错了。

三、这里只讲管脚未定义的情况

因为位置变了，布局布线也需要改变。如果这个管脚的功能是需要的，那我们只能重新Implementation；如果这个管脚功能是不需要的，那这个管脚我们可以先不定义，我们可以按照以下步骤在不重新Implentation的情况下生成bit：

1、我们可以在工程文件夹内新建一个.txt文本文件,在文件中写入以下命令,保存并将文件后缀名改为.tcl：

set_property IS_ENABLED 0 [get_drc_checks NSTD-1]
set_property IS_ENABLED 0 [get_drc_checks UCIO-1]

2、在vivado界面中，点击Flow Navigator —— PROJECT MANAGER下面的setting，如下图所示：

Vivado Error问题之[DRC NSTD-1][DRC UCIO-1] FPGA管脚约束问题导致生成bit时报错，如何在不重新Implentation情况下生成bit？,Vivado常见error,fpga开发,fpga

3、在弹出的1号标记的Settings界面中，找到标记“project settings”目录下的2号标记“Bitstream”，点击在4号标记后面的“…”把相应路径下的的“.tcl”文件添加到3号标记的tcl.pre参数下，然后点击“Apply”按钮,再点击“OK”按钮即可，如下图所示： Vivado Error问题之[DRC NSTD-1][DRC UCIO-1] FPGA管脚约束问题导致生成bit时报错，如何在不重新Implentation情况下生成bit？,Vivado常见error,fpga开发,fpga

4、点击左侧的“Generate Bitstream”按钮；

这样就可以不用重新综合实现直接生成bit文件了。文章来源地址https://www.toymoban.com/news/detail-804972.html

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