FPGA引脚物理电平（内部资源，Select IO）-认知2-Toy模板网

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引脚电平
The SelectIO pins can be configured to various I/O standards, both single-ended and differential.
• Single-ended I/O standards (e.g., LVCMOS, LVTTL, HSTL, PCI, and SSTL)
• Differential I/O standards (e.g., LVDS, Mini_LVDS, RSDS, PPDS, BLVDS, and differential HSTL and SSTL)
引脚种类
VCCO，for PL
每个Bank对应一个电压，HP Bank VCCO电压应该小于<=1.8V.
The VCCO supply is the primary power supply of the 7 series I/O circuitry

Vref,
Single-ended I/O standards with a differential input buffer require an input reference voltage (VREF).

VccAux,
FPGA引脚物理电平（内部资源，Select IO）-认知2,FPGA,fpga开发

FPGA引脚物理电平（内部资源，Select IO）-认知2,FPGA,fpga开发
VCCAux_IO,
The auxiliary I/O (VCCAUX_IO) supply rail is only present in HP I/O banks and provides power to the I/O circuitry.

引脚配置资源
3.1，DCI，
3.2， IN_TERM,
Uncalibrated Split Termination in High-Range I/O Banks (IN_TERM）
引脚电平
电平标准网站：https://www.jedec.org/
LVTTL, low voltage ttl, 3.3V.
LVCMOS, Low voltage cmos, LVCMOS12,LVCMOS18,LVCMOS25,LVCMOS33
LVDCI/2 (Low-Voltage Digitally Controlled Impedance)
HSLVDCI (High-Speed LVDCI)
HSTL (High-Speed Transceiver Logic), HSTL_ I_12, HSTL_ I_18,HSTL_ I_DCI,DIFF_HSTL_I a
SSTL (Stub-Series Terminated Logic)
LVDS and LVDS_25 (Low Voltage Differential Signaling)
RSDS (Reduced Swing Differential Signaling)