「HDLBits题解」Counters-Toy模板网

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本专栏的目的是分享可以通过HDLBits仿真的Verilog代码以提供参考各位可同时参考我的代码和官方题解代码或许会有所收益

题目链接：Count15 - HDLBits

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q
); 
    always @(posedge clk) begin
        if (reset) q <= 0 ; 
        else q <= q == 15 ? 0 : q + 1 ; 
    end

endmodule

题目链接：Count10 - HDLBits

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q
); 
    always @(posedge clk) begin
        if (reset) q <= 0 ; 
        else q <= q == 9 ? 0 : q + 1 ; 
    end

endmodule

题目链接：Count1to10 - HDLBits

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output reg [3:0] q
); 
    always @(posedge clk) begin
        if (reset) q <= 1 ; 
        else q <= q == 10 ? 1 : q + 1 ; 
    end

endmodule

题目链接：Countslow - HDLBits

module top_module (
    input clk,
    input slowena,
    input reset,
    output reg [3:0] q
);
    always @(posedge clk) begin
        if (reset) q <= 0 ; 
        else if (slowena) q <= q == 9 ? 0 : q + 1 ; 
        else q <= q ; 
    end

endmodule

题目链接：Exams/ece241 2014 q7a - HDLBits

module top_module (
    input clk,
    input reset,
    input enable,
    output reg [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); 
    reg [3:0] cnt_4o ;

    always @(posedge clk) begin
        if (reset) Q <= 1 ; 
        else if (enable) Q <= Q == 12 ? 1 : Q + 1 ;
        else Q <= Q ; 
    end

    assign c_enable = enable ; 
    assign c_load = reset | (enable && Q == 12) ; 
    assign c_d = c_load ? 1 : 0 ; 

    count4 the_counter (clk, c_enable, c_load, c_d, cnt_4o);

endmodule

题目链接：Exams/ece241 2014 q7b - HDLBits

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); 
    reg [3:0] q0, q1, q2 ;

    bcdcount counter0 (clk, reset, c_enable[0], q0);
    bcdcount counter1 (clk, reset, c_enable[1], q1);
    bcdcount counter2 (clk, reset, c_enable[2], q2);

    assign c_enable = {q0 == 9 & q1 == 9, q0 == 9, 1'b1}; 
    assign OneHertz = q2 == 9 & q1 == 9 & q0 == 9 ; 

endmodule

题目链接：Countbcd - HDLBits

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output reg [15:0] q
);
    always @ (*) begin 
        if (q[3:0] == 9 && q[7:4] == 9 && q[11:8] == 9) ena = 7 ; 
        else if (q[3:0] == 9 && q[7:4] == 9) ena = 3 ; 
        else if (q[3:0] == 9) ena = 1 ; 
        else ena = 0 ;
    end

    sub_cnt u1(clk, reset, 1'b1, q[3:0]) ;
    sub_cnt u2(clk, reset, ena[1], q[7:4]) ;
    sub_cnt u3(clk, reset, ena[2], q[11:8]) ;
    sub_cnt u4(clk, reset, ena[3], q[15:12]) ;

endmodule 
       
module sub_cnt (
    input clk,
    input reset,      // Synchronous active-high reset
    input enable, 
    output reg [3:0] q
); 
    always @(posedge clk) begin
        if (reset) q <= 0 ; 
        else if (enable) q <= q == 9 ? 0 : q + 1 ; 
        else q <= q ; 
    end

endmodule

题目链接：Count clock - HDLBits文章来源地址https://www.toymoban.com/news/detail-818969.html

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss
); 
    wire [2:0] enable ; 

    assign enable = {mm == 8'h59 & ss == 8'h59 & ena, ss == 8'h59 & ena, ena} ; 

    cnt60 uss(clk, reset, enable[0], ss) ; 
    cnt60 umm(clk, reset, enable[1], mm) ; 

    always @(posedge clk) begin
        if (reset) begin 
            hh <= 8'h12 ; 
            pm <= 0 ; 
        end
        else 
            if (enable[2]) 
                if (hh == 8'h12) hh <= 8'h1 ; 
                else if (hh == 8'h11) begin 
                    pm <= ~pm ; 
                    hh[3:0] <= hh[3:0] + 1'h1 ; 
                end
                else 
                    if (hh[3:0] == 4'h9) begin 
                        hh[3:0] <= 4'h0 ; 
                        hh[7:4] <= hh[7:4] + 1'h1 ; 
                    end
                    else 
                        hh[3:0] <= hh[3:0] + 1'h1 ; 
            else 
                hh <= hh ;
    end
endmodule

module cnt60(
    input clk, 
    input reset, 
    input ena, 
    output reg [7:0] q 
);
    always @(posedge clk) begin
        if (reset) q <= 8'h0 ; 
        else 
            if (ena) 
                if (q[3:0] == 4'h9) 
                    if 
                        (q[7:4] == 4'h5) q <= 8'h0 ; 
                    else begin 
                        q[7:4] <= q[7:4] + 1'h1 ; 
                        q[3:0] <= 4'h0 ; 
                    end
                else 
                    q[3:0] <= q[3:0] + 1'h1 ; 
            else 
                q <= q ; 
    end
endmodule

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