HDLbits counters 12 hour clock-Toy模板网

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module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    wire en,en1;
    reg [3:0]ss_one,ss_ten,mm_one,mm_ten,hh_one,hh_ten;
    always@(posedge clk)
        begin
            if(reset)
                begin
                    ss_one <= 4'd0;
                end
            else if(ena == 4'd1 && ss_one <= 4'd8)
                begin
                    ss_one <= ss + 4'd1;           
                end
            else if (ena == 4'd1 && ss_one == 4'd9)
                begin
                    ss_one <= 4'd0;     
                end
        end
    
    always@(posedge clk)
        begin
            if(reset)
                begin
                    ss_ten <= 4'd0;
                end
            else if (ena == 4'd1 && ss_ten <= 4'd4 && ss_one == 4'd9)
                begin
                    ss_ten <= ss_ten + 4'd1;
                end
            else if (ena == 4'd1 && ss_ten == 4'd5 && ss_one == 4'd9 )
                begin
                    ss_ten <= 4'd0;                   
                end
        end
  
    always@(posedge clk)
        begin
            if(reset)
                begin
                    mm_one <= 4'd0;
                end
            else if (en == 1 && mm_one <= 4'd8)
                begin
                    mm_one <= mm_one + 4'd1;                    
                end
            else if (en == 1 && mm_one == 4'd9)
                 begin
                    mm_one <= 4'd0;                    
                end
        end

    always@(posedge clk)
        begin
            if(reset)
                begin
                    mm_ten <= 4'd0;
                end
            else if (en == 1 && mm_ten <= 4'd4&& mm_one == 4'd9)
                begin
                    mm_ten <= mm_ten + 4'd1;
                end
            else if (en == 1 && mm_ten == 4'd5 && mm_one == 4'd9)
                begin
                    mm_ten <= 4'd0;
                end
                
        end

    always@(posedge clk )
        begin
            if(reset)
                begin
                    hh_one <= 4'd2;
                end
            else if (en1 == 1  && hh_ten ==4'd0 && hh_one <=4'd8)
                begin
                    hh_one <= hh_one + 4'd1;
                end
            else if (en1 == 1  && hh_ten ==4'd0 && hh_one ==4'd9)
                begin
                    hh_one <= 4'd0;                    
                end
            else if (en1 == 1 && hh_ten ==4'd1 &&  hh_one <=4'd1 )
                begin
                    hh_one <= hh_one + 4'd1;
                end
            else if (en1 == 1 && hh_ten ==4'd1 &&  hh_one ==4'd2)
                begin
                    hh_one <= 4'd1;        
                end

        end
    
    always@(posedge clk )
        begin
            if(reset)
                begin
                    hh_ten <= 4'd1;                    
                end
            else if(en1 == 1 && hh_one == 4'd9 && hh_ten == 4'd0)
                begin
                    hh_ten <=  4'd1;                         
                end
            else if (en== 1 && en1 == 1 && hh_one == 4'd2 && hh_ten == 4'd1)
                begin
                    hh_ten <= 4'd0;                       
                end
            else 
                begin
                    hh_ten <= hh_ten;                       
                end
        end
    
    always@(posedge clk)
        begin
            if(reset)
                begin
                    pm <= 1'd0;
                end
            else if (hh_ten == 4'd1 && hh_one == 4'd1 &&mm_ten == 4'd5 && mm_one == 4'd9 && ss_ten == 4'd5 && ss_one == 4'd9)
                begin
                    pm <= ~pm;                    
                end
            else  
                begin
                    pm<= pm;
                end
        end
                    
    assign ss = {ss_ten,ss_one};
    assign mm = {mm_ten,mm_one};
    assign hh = {hh_ten,hh_one};
    assign en = (ss_ten == 4'd5 && ss_one == 4'd9 )?1:0;
    assign en1 = (mm_ten == 4'd5 && mm_one == 4'd9 && ss_ten == 4'd5 && ss_one == 4'd9)?1:0;

endmodule

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