名称:基于FPGA的3位二进制的乘法器VHDL代码Quartus 开发板(文末获取)
软件:Quartus
语言:VHDL
代码功能:
3位二进制的乘法器
该乘法器实现两个三位二进制的乘法,二极管LED2~LED0显示输入的被乘数,LED5~LED3显示乘数,数码管显示相应的十进制输入值和输出结果
本代码已在开发板验证,开发板如下,其他开发板可以修改管脚适配:
1. 工程文件
2. 程序文件
3. 程序编译
4. 管脚分配
5. RTL图
6. 仿真图
部分代码展示:文章来源:https://www.toymoban.com/news/detail-831824.html
LIBRARY ieee; USE ieee.std_logic_1164.all; --乘法器 ENTITY mult IS PORT ( clk_in : IN STD_LOGIC;--时钟 reset_n : IN STD_LOGIC;--复位 data_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--输入 key1_n : IN STD_LOGIC;--按键1 key2_n : IN STD_LOGIC;--按键2 key_enter_n : IN STD_LOGIC;--等于键 LED1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);--数据1 LED2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);--数据2 bit_select : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--数码管位选 seg_select : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--数码管段选 ); END mult; ARCHITECTURE behave OF mult IS --控制模块 COMPONENT state_ctrl IS PORT ( clk_in : IN STD_LOGIC; reset_n : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); key1_n : IN STD_LOGIC; key2_n : IN STD_LOGIC; key_enter_n : IN STD_LOGIC; data_1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); data_2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); data_result : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END COMPONENT; --显示模块 COMPONENT display IS PORT ( clk : IN STD_LOGIC; data_1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--乘数1 data_2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--乘数2 data_result : IN STD_LOGIC_VECTOR(5 DOWNTO 0);--乘积 bit_select : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--数码管位选 seg_select : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--数码管段选 ); END COMPONENT; SIGNAL data_1 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL data_2 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL data_result : STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN --控制模块 i_state_ctrl : state_ctrl PORT MAP ( clk_in => clk_in, reset_n => reset_n, data_in => data_in, key1_n => key1_n, key2_n => key2_n, key_enter_n => key_enter_n, data_1 => data_1, data_2 => data_2, data_result => data_result ); --LED指示灯 LED1<=data_1; LED2<=data_2; --显示模块 i_display : display PORT MAP ( clk => clk_in, data_1 => data_1, data_2 => data_2, data_result => data_result, bit_select => bit_select, seg_select => seg_select ); END behave;
源代码
扫描文章末尾的公众号二维码文章来源地址https://www.toymoban.com/news/detail-831824.html
到了这里,关于基于FPGA的3位二进制的乘法器VHDL代码Quartus 开发板的文章就介绍完了。如果您还想了解更多内容,请在右上角搜索TOY模板网以前的文章或继续浏览下面的相关文章,希望大家以后多多支持TOY模板网!