AXI4-Full Xilinx FPGA使用理解---信号定义理解-Toy模板网

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一、AXI4

signal	dir	Xilinx	中文理解
ID类
AWID	M2S	Masters need only output the set of ID bits that it varies (if any) to indicate re-orderable transaction threads. Single-threaded master interfaces can omit this signal. Masters do not need to output the constant portion that comprises the Master ID, as this is appended by the AXI Interconnect.	当只有一个主接口时无需关心此接口，当有多个主接口时也可把它设置成一个固定值，当有多个主时这个也可设置成一个固定值，实际输出给DDR的AWID由AXI Interconnect给出。
BID	S2M	See AWID for more information.	wirte response channel
ARID	M2S	Masters need only output the set of ID bits that it varies (if any) to indicate re-orderable transaction threads. Single-threaded master interfaces can omit this signal. Masters do not need to output the constant portion that comprises the “Master ID”, as this is appended by the AXI Interconnect.	使用方式同AWID
RID	M2S	See ARID for more information.	同ARID一致
region类
AWREGION	M2S	Can be implemented in Xilinx Endpoint slave IP. Not present on master IP. Generated by AXI Interconnect using corresponding address decoder range settings.	区域标识符，允许一个从设备的单个物理接口用作多个逻辑接口，一般设置为4‘b0000
ARREGION	M2S	Can be implemented in Xilinx Endpoint Slave IP. Not present on master IP. Generated by AXI Interconnect using corresponding address decoder range settings.	区域标识符，允许一个从设备的单个物理接口用作多个逻辑接口，一般设置为4‘b0000
lock类
AWLOCK	M2S	Exclusive access support not implemented in endpoint Xilinx IP. Infrastructure IP will pass exclusive access bit across a system.	这个信号在AXI3协议中用于锁定从机占用总线，但在AXI4中取消了相关支持，仅留下一位信号用作指示为正常传输(1'b0)，还是独有传输(1'b1),一般设置为1’b0
ARLOCK	M2S	Exclusive access support not implemented in Endpoint Xilinx IP. Infrastructure IP passes exclusive access bit across a system.	这个信号在AXI3协议中用于锁定从机占用总线，但在AXI4中取消了相关支持，仅留下一位信号用作指示为正常传输(1'b0)，还是独有传输(1'b1),一般设置为1’b0
CACH类
AWCACH	M2S	0011 value recommended. Xilinx IP generally ignores (as slaves) or generates (as masters) transactions as Normal, Non-cacheable, Modifiable, and Bufferable. Infrastructure IP will pass Cache bits across a system.	xilinx建议此值给0011也有一些资料建议此值给0010(不使用cache补使用buff)
ARCACH	M2S	0011 value recommended. Xilinx IP generally ignores (as slaves) or generates (as masters) transactions with Normal, Non-cacheable, Modifiable, and Bufferable. Infrastructure IP will pass Cache bits across a system.	xilinx建议此值给0011也有一些资料建议此值给0010(不使用cache补使用buff)
PROT(权限控制)
AWPROT	M2S	000 value recommended. Xilinx IP generally ignores (as slaves) or generates transactions (as masters) with Normal, Secure, and Data attributes. Infrastructure IP passes Protection bits across a system.
ARPROT	M2S	Xilinx IP generally ignore (as slaves) or generate transactions (as masters) with Normal, Secure, and Data attributes. Infrastructure IP passes Protection bits across a system. 000 value recommended.
QOS
AWQOS	M2S	Not implemented in Xilinx Endpoint IP. Infrastructure IP passes QoS bit across a system.	xilinx AXI4不支持设置为0
ARQOS	M2S	Not implemented in Xilinx Endpoint IP. Infrastructure IP passes QoS bit across a system	xilinx AXI4不支持设置为0
USER
AWUSER	M2S	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP passes USER bits across a system.	xilinx AXI4不支持设置为0
WUSER	M2S	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP will pass USER bits across a system.	xilinx AXI4不支持设置为0
BUSER	S2M	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP will pass USER bits across a system.	来自写相应通道， xilinx AXI4不支持。
ARUSER	M2S	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP passes USER bits across a system.	xilinx AXI4不支持设置为0
RUSER	S2M	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP will pass USER bits across a system.	xilinx AXI4不支持
地址写
AWADDR	M2S	Widths up to 64 bits. High-order bits outside the native address range of a slave are ignored (trimmed), by an endpoint slave, which could result in address aliasing within the slave.	写地址。写地址给出突发数据传输的第一个传输地址。
AWLEN	M2S	Support bursts: • Up to 256 beats for incrementing ( INCR ). • 16 beats for WRAP .	突发长度。给出突发传输中准确的传输个数。支持INCR和WRAP传输模式。突发长度=awlen+1
AWSIZE	M2S	Transfer width 8 to 1024 bits supported. Use of narrow bursts where AWSIZE is less than the native data width is not recommended.	突发大小。这个信号用于确定突发传输中每个传输的大小。总线位宽=2^size Betyes(例如总线位宽为512bit，则AWSIZE为6),指示有效字节数，如果位宽为512bit,但有效位宽为32bit则此位填2
AWBURST	M2S	INCR and WRAP fully supported. FIXED bursts are not recommended. Conversions of FIXED bursts through AXI Interconnect infrastructure may have sub-optimal performance.	00:FIXED 01:INCR 10:WRAP 11:保留
AWVALID	M2S	Fully supported	主设备给出的地址和相关控制信号有效
AWREADY	S2M	Fully supported	从设备已准备好接收地址和相关的控制信号
数据写
WDATA	M2S	Native width 32 to 1024 bits supported.	写数据，32位到1024位宽
WSTRB	M2S	Fully supported.	写字节选通，用于表示更新存储器的字节通道，对于数据总线的每8位数据有一位写选通信号。
WLAST	M2S	Fully supported.	写最后一个数据指示信号。表示突发传输中的最后一个数据。
WVALID	M2S	Fully supported.	写有效。为高指示数据有效。
WREADY	S2M	Fully supported.	写准备。为高表示从设备空闲，准备接收数据；为低表示从设备忙
写响应
BRESP	S2M	Fully supported.	指示写的结果 00:OKAY 正常访问成功，还可以指示独占访问失败。 01：EXOKAY指示独占访问的部分已成功。 10：SLVERR主机正常发送但是从机没有正常接收。 11：DECERR主机没找到从机
BVALID	S2M	Fully supported.	写响应有效。为高指示响应数据有效。
BREADY	M2S	Fully supported.	写响应准备。为高表示主设备空闲，准备接收写响应；为低表示主设备忙。
读地址
ARADDR	M2S	Widths up to 64 bits. High-order bits outside the native address range of a slave are ignored (trimmed) by an endpoint slave, which could result in address aliasing within the slave.	读地址。读地址给出突发数据传输的第一个传输地址。
ARLEN	M2S	Support bursts: • Up to 256 beats for incrementing ( INCR ). • 16 beats for WRAP .	突发长度。给出突发传输中准确的传输个数。支持INCR和WRAP传输模式。
ARSIZE	M2S	Transfer width 8 to 1024 bits supported. Use of narrow bursts where ARSIZE is less than the native data width is not recommended.	突发大小。这个信号用于确定突发传输中每个传输的大小。，定义和AWSIZE相同。
ARBURST	M2S	INCR and WRAP fully supported. FIXED bursts are not recommended. Conversions of FIXED bursts through AXI Interconnect infrastructure may have sub-optimal performance.	突发类型。该信息与突发大小信息一起，表示在突发过程中，地址如何应用于每个传输。支持INCR和WRAP传输模式。
ARVALID	M2S	Fully supported.	读地址有效信号。为高指示地址有效。
ARREADY	S2M	Fully supported.	读地址准备信号。为高表示从设备空闲，准备接收地址；为低表示从设备忙。
读数据
RDATA	S2M	Native width 32 to 1024 bits supported.	读数据。32位到1024位宽
RRESP	S2M	Fully supported.	读响应。该信号表示读状态，可允许相应的表示为OKAY\EXOKAY\SLVERR\DECERR。
RLAST	S2M	Fully supported.	读最后一个数据指示信号。表示突发传输中的最后一个数据。
RVALID	S2M	Fully supported.	读有效。为高指示数据有效。
RREADY	M2S	Fully supported.	读准备。为高表示主设备空闲，准备接收数据；为低表示主设备忙。

二. AXI4_Lite

写地址
signal	direction	中文理解
AWADDR	M2S	写地址不支持burst传输
AWPROT	M2S	000 value recommended.详情见AXI4
AWVALID	M2S	主设备给出的地址和相关控制信号有效
AWREADY	S2M	从设备已准备好接收地址和相关的控制信号
写数据
WDATA	M2S	写数据，近支持32bit位宽
WSTRB	M2S	写字节选通信号，从设备可选择忽略
WVALID	M2S	写有效。为高指示数据有效。
WREADY	S2M	写准备。为高表示从设备空闲，准备接收数据；为低表示从设备忙。
写响应
BRESP	S2M	EXOKAY状态不支持
BVALID	S2M	写响应有效。为高指示响应数据有效。
BREADY	M2S	写响应准备。为高表示主设备空闲，准备接收写响应；为低表示主设备忙。
读地址
ARADDR	M2S	读地址
ARPROT	M2S	000 value recommended.详情见AXI4
ARVALID	M2S	读地址有效信号。为高指示地址有效。
ARREADY	S2M	读地址准备信号。为高表示从设备空闲，准备接收地址；为低表示从设备忙。
读数据
RDATA	S2M	读数据，指支持32bit位宽
RRESP	S2M	读响应，不支持EXOKAY
RVALID	S2M	读有效。为高指示数据有效。
RREADY	M2S	读准备。为高表示主设备空闲，准备接收数据；为低表示主设备忙。